IP based configurable SIMD massively parallel SoC

Mouna Baklouti (1) , Philippe Marquet (1, 2) , Jean-Luc Dekeyser (1, 2) , Mohamed Abid (3, 4)

1 DART - Contributions of the Data parallelism to real time
2 LIFL - Laboratoire d'Informatique Fondamentale de Lille
3 CEM Lab - ENIS - Département de Génie Électrique de Sfax [ENIS]
4 CES Lab - Computer & Embedded Systems

Significant advances in the field of configurable computing have enabled parallel processing within a single Field- Programmable Gate Array (FPGA) chip. This paper presents the implementation of a flexible and programmable Single Instruc- tion Multiple Data (SIMD) processing system on FPGA that can be adapted to the application. Its implementation is based on an IP (Intellectual Property) assembling approach making its design fast and easy. A generation tool is also developed to generate the SIMD configuration depending on the application requirements. The proposed parallel processing system on chip is portable, scalable and flexible since it can be customized to match the needs of a data parallel application. Based on FPGA, different SIMD configurations have been evaluated in terms of performance and area trade-offs. The proposed parametric system shows good results executing some signal processing applications such as parallel matrices multiplication, FIR filter and RGB to YIQ image color conversion.

Domaines: Systèmes embarqués

Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid. IP based configurable SIMD massively parallel SoC. 20th International Conference on Field Programmable Logic and Applications, FPL 2010, Aug 2010, Milano, Italy. ⟨inria-00525333⟩