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Allocating Registers in Multiple Instruction-Issuing Processors

Abstract : This work addresses the problem of scheduling a basic block of operations on a multiple instruction-issuing processor. We show that integrating register constraints into operation sequencing algorithms is a complex problem in itself. Indeed, while scheduling a forest of unit time operations on a processor with $P$ parallel instruction slots can be solved in polynomial time, the problem becomes NP-hard when $P$ is unbounded but only $R$ registers are available. As a result we have devised a concise integer linear programming formulation of this scheduling problem that accounts for both register and instruction issuing constraints. This allows the use of off-the-shelf routines to find optimum solutions, which can then be compared with the results obtained by polynomial-time heuristics. Two such heuristics are given, and their combined results are shown to be optimal in 99.5% of the cases for trees of height at most 6. A byproduct of these experiments is to show that our integer programming formulation is quite practical as it can find an optimum solution for a tree of height 6 in roughly 0.1 seconds on a sparc workstation.
Document type :
Reports (Research report)
Domain :

Cited literature [2 references]

https://hal.inria.fr/inria-00074059
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Submitted on : Wednesday, May 24, 2006 - 2:24:23 PM
Last modification on : Wednesday, October 26, 2022 - 8:16:09 AM
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• HAL Id : inria-00074059, version 1

Citation

Christine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn. Allocating Registers in Multiple Instruction-Issuing Processors. [Research Report] RR-2628, INRIA. 1995. ⟨inria-00074059⟩

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