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Polychrony for system design

Abstract : System design based on the so-called «synchronous hypothesis» consists of abstracting non-functional implementation details of a system and lets one benefit from a focused reasoning on the logics behind the instants at which system functionalities should be secured, providing ease to generating synchronous circuits and verifying their functionalities using compilers and tools that implement this approach. In the relational model of the design language Signal, this affinity goes beyond the domain of purely synchronous circuits and embraces the context of complex architectures consisting of synchronous circuits and desynchronization protocols: Gals architectures. The unique features of Signal are to provide the notion of polychrony: the capability to describe circuits and systems with several clocks; to support refinement: the ability to assist and support system design from the early stages of requirement specification, to the later stages of synthesis and deployment. The Signal model provides a design methodology that forms a continuum from synchrony to asynchrony, from specification to implementation , from abstraction to concretization, from interfaces to implementations. Signal gives the opportunity to seamlessly model circuits and devices at multiple levels of abstractions, by implementing mechanisms found in many hardware simulators, while reasoning within a simple and formally defined mathematical model. In the same manner, the flexibility inherent to the abstract notion of signal handled in the polychronous design model of Signal invites and favors the design of correct by construction systems by means of well-defined transformations of system specifications that preserve the intended semantics and stated properties of the architecture under design. The aim of the present article is to review and summarize these formal, correct-by-construction, design transformations. Most of them are implemented in the Polychrony tool-set, allowing for mixed bottom-up and top-down design of embedded hardware-software system using the Signal design language.
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Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 7:03:58 PM
Last modification on : Friday, July 10, 2020 - 4:22:09 PM
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  • HAL Id : inria-00071871, version 1


Paul Le Guernic, Jean-Pierre Talpin, Jean-Christophe Le Lann. Polychrony for system design. [Research Report] RR-4715, INRIA. 2003. ⟨inria-00071871⟩



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