Charge Transport Across Au–P3HT–Graphene van der Waals Vertical Heterostructures

Hybrid van der Waals heterostructures based on 2D materials and/or organic thin films are being evaluated as potential functional devices for a variety of applications. In this context, the graphene/organic semiconductor (Gr/OSC) heterostructure could represent the core element to build future vertical organic transistors based on two back-to-back Gr/OSC diodes sharing a common graphene sheet, which functions as the base electrode. However, the assessment of the Gr/OSC potential still requires a deeper understanding of the charge carrier transport across the interface as well as the development of wafer-scale fabrication methods. This work investigates the charge injection and transport across Au/OSC/Gr vertical heterostructures, focusing on poly(3-hexylthiophen-2,5-diyl) as the OSC, where the PMMA-free graphene layer functions as the top electrode. The structures are fabricated using a combination of processes widely exploited in semiconductor manufacturing and therefore are suited for industrial upscaling. Temperature-dependent current–voltage measurements and impedance spectroscopy show that the charge transport across both device interfaces is injection-limited by thermionic emission at high bias, while it is space charge limited at low bias, and that the P3HT can be assumed fully depleted in the high bias regime. From the space charge limited model, the out-of-plane charge carrier mobility in P3HT is found to be equal to μ ≈ 2.8 × 10–4 cm2 V–1 s–1, similar to the in-plane mobility reported in previous works, while the charge carrier density is N0 ≈ 1.16 × 1015 cm–3, also in agreement with previously reported values. From the thermionic emission model, the energy barriers at the Gr/P3HT and Au/P3HT interfaces result in 0.30 eV and 0.25 eV, respectively. Based on the measured barriers heights, the energy band diagram of the vertical heterostructure is proposed under the hypothesis that P3HT is fully depleted.

wafer, which is pre-cleaned in oxygen plasma (600 W for 5 min). The electrodes (Ti/Au) are deposited by e-beam physical vapour deposition (EBPVD) and patterned by lift-off in DMSO at 100°C for 30 min. The resist for the lift-off (AZ2020nlof) is spin-coated (4000 rpm for 60 s), exposed to UV light (lamp intensity 11 mW/cm 2 ) through an optical mask, and then developed (AZ726mif, 35 s).

b) Preparation of the lift-off resist
The chip with pre-patterned electrodes (Si/SiO2/Ti/Au) is ultra-sonicated in Acetone for 5 min, rinsed with IPA and blown dry with nitrogen. Then, it is exposed to oxygen plasma at 600 W for 5 min. After HMDS treatment, the chip is coated with a double layer positive optical resist: first, the chip is spin-coated with a LOR5B resist (4000 rpm, 40 s) and backed at 180°C for 5 min. Then, it is spin-coated with an AZ1505 positive resist (4000 rpm, 40 s) and backed at 110°C for 1 min. The device area is exposed for 1.8 s to UV light (lamp intensity 11 mW/cm 2 , dose 20 mJ) through an optical mask. Finally, the exposed resist is developed in AZ400K (400K:DIW, 1:4) for 25 s and rinsed with de-ionized water.

c) P3HT deposition and patterning
A 100 nm film of P3HT is obtained by spin-coating 10 mg/ml solution of P3HT in chlorobenzene (1000 rpm for 60 s) on the substrate. Subsequently, the P3HT film is patterned by lift-off in DMSO (5 min). The chip is then rinsed in de-ionized water, blown dry with nitrogen and finally annealed overnight at 110°C in vacuum (~1mbar).

e) PMMA removal from graphene
The chip is annealed overnight at 80°C in vacuum (~1 mbar). The top PMMA layer is removed in Acetone (5 min) and the chip annealed again overnight at 80°C in vacuum (~1 mbar).

f) RIE patterning of the graphene top electrode
The chip is first spin-coated with a 50K PMMA resist (AR-P 632.06, 4000 rpm for 60 s), then with an AZ1505 optical resist (4000 rpm, 40 s) and backed at 110°C for 1 min. The device area is exposed for 1.8 s to UV light (lamp intensity 11 mW/cm2) through an optical mask.
The exposed optical resist is developed in AZ400K (400K:DIW, 1:4) for 15 s and rinsed with de-ionized water. Then, RIE is used to remove the first layer of PMMA 50K and graphene (O2, 30 sccm, 25 W).

g) PMMA/Optical resist removal from graphene
The PMMA/Optical resist protecting the graphene electrode is removed with Acetone (1 min), then the chip is rinsed in de-ionized water and blown dry with nitrogen.    The dielectric constant of P3HT for different devices is calculated using the parallel plate capacitor equation (Eq. S1). The results are shown in Table 1.

FIB/SEM/AFM Characterization
= 0 Eq. S1 Where 0 is the vacuum permittivity, A is the device area and t the device thickness. The propagation errors at first order is calculates as shown in Eq. S2.
Where Δ is the fit error, Δ = 30 nm is the estimation of the thickness error and Δ = (( − ) 2 ⁄ ) 2 is the estimation of the area error. Where and are the diameter of the gold and graphene electrodes, respectively.
12 Figure S7. SCL and TE models fitting for different device with diameters: (a-b) 5 μm, (c-d) 15 μm, (e-f) 25 μm, and (g-h) 50 μm. Table 1 shows the statistic of fitting parameters. (a-b) In Fig.   S2, one can observe a slightly thicker organic layer around the edge of the devices active area.
The latter could have affect the actual average thickness of small devices. To take this effect into account, the thickness of the 5 μm and 10 μm device was set to 130 nm and 120 nm. For all the other devices, where the edge area can be neglected compared to the whole device area, the thickness was set to 100 nm.  smaller. This can be ascribed to the fact that the I-V measurements were done in vacuum after annealing. In this latter case, the obtained potential barriers at the interfaces are larger than the ones obtained from KPFM measurements done in air and ambient condition.  Table S1. Overview of the entire chip. Green cases show the working devices, while the red cases are the not working ones. Roughly, 50% of the chip devices are working and show the same J-V behavior of the device shown in Fig. 5.

Space-charge limited (SCL) current modeling
The analytical solution of the space-charge limited (SCL) current is here reported for convenience, as proposed in previous works. [1][2][3][4] 1) From the continuity equation: and the Poisson equation: 2) Assuming that the diffusion current is negligible 3 : 3) Integrating Eq. S5: where K is a constant.
5) K' is found using the boundary conditions at the injecting contact (x = 0). Defining | = 0 = 0 and applying the Dirichlet boundary condition ( ) Eq. S8 6) Then, plugging K' in Eq. S7: Finally, the voltage associated to the current J in the semiconductor of length L is given by: Eq. S10 8) The current-voltage relation is found solving Eq. S10 for the current. Two solutions are found: for K' << L Eq. S11 = 0 for K' >> L Eq. S12 J is the current density driven through the device by applying the bias V. The other parameters are defined by the semiconductor properties. N0, that it the charge carrier density at the interface, is defined by the density of states of the semiconductor NDOS and by the potential barrier height Φ at the interface: The case of a 20 μm representative device shown in Fig. 5 is considered. N0 at the Gr/P3HT interface can be measured by (i) extracting the hole mobility of P3HT using Eq. S11 for negative biases and (ii) applying Eq. S12 in the linear region for positive biases. The obtained charge carrier density at the Gr/P3HT interface is N0 = 1.1 x 10 15 cm -3 .
Then, using the potential barrier height (0.31 eV, extracted from TE model) and N0 at the Gr/P3HT interface, NDOS of P3HT can be calculated: NDOS = 2.4 x 10 20 cm -3 . Finally, N0 at the Au/P3HT can be computed using Eq. S11 and the potential barrier height (0.25 eV). Obtained charge carrier density at the Au/P3HT interface is N0 = 1.2 x 10 16 cm -3 . It is worth observing that the imagecharge induced lowering of potential barrier is not considered. N0 may depend on the applied bias and be larger than the estimated value 1 . Figure S10