La2NiO4+δ‐Based Memristive Devices Integrated on Si‐Based Substrates

Valence change memories, in which internal redox reactions control the change in resistance are promising candidates for resistive random access memories (ReRAMs) and neuromorphic computing elements. In this context, La2NiO4+δ (L2NO4), a mixed ionic‐electronic conducting oxide, well known for its highly mobile oxygen interstitial ions, emerges as a potential switching material for novel L2NO4‐based memristive devices. However, their integration in complementary metal oxide semiconductor (CMOS) technology still has to be demonstrated, as the major focus of previous studies has been carried out on epitaxial films grown on single crystals. In this work, the optimization of the deposition temperature and precursor solution composition is presented, allowing to obtain high‐quality polycrystalline L2NO4 thin films grown by metal organic chemical vapor deposition on a platinized silicon substrate, and to use these films to build memristive devices in vertical configuration with Ti top electrodes. A bipolar analog‐type transition in resistance can be achieved in Ti/L2NO4/Pt memristive devices. While the “forming” process required for the devices based on nonoptimized L2NO4 thin films is considered as a drawback, the Ti/optimized L2NO4/Pt devices are forming‐free and exhibit a good cyclability. These results prove the switching response of L2NO4‐based devices in a vertical configuration for the first time.


Introduction
Resistive switching (RS) is described as the phenomena taking place in capacitorlike heterostructures (typically metal/insulator (or semiconductor)/metal stacks), in which resistance can be switched between a low resistance state (LRS) and a high resistance state (HRS) upon an appropriate applied electric field. [1] The study of RS on memristive devices has attracted considerable interest for redox-based resistive random access memory (ReRAM) applications since the reversible resistance change can be used to store logic states (e.g., values "0" and "1" of the binary system), as well as for other logic elements in novel computing paradigms. [2][3][4][5][6][7] In addition, in some cases, by applying suitable voltage pulses of controlled amplitude and duration, several different resistance states of the ReRAM cell can be written, read, and erased, which paves the way for multilevel cell memories. Besides, a strong renewal of interest for non-von Neumann computing architecture has recently led to the development of solid state-based synapses dedicated to neuromorphic computing applications using memristive oxides as active layers. [8][9][10][11][12] Oxide-based valence-change memories (VCMs), in which a field-driven oxygen motion triggers the resistance switching of the device by internal redox reactions (the local change of valence in the cation sublattice), are one of the most promising candidates for memory and artificial synapse applications. The valence change can occur in localized regions (filament-type RS) or over the entire memristor area (interface-type RS). Although the most common VCMs are based on filament-type switching, there are still challenging issues to overcome, such as variability, forming, etc. [13] In fact, the forming process is a prerequisite step, in which a relatively high electric field is applied to create the filament. This process is considered as a soft breakdown of the switching layer and is usually required before the memory cell works at a lower voltage. In addition, as the formation of the filament is a stochastic process, the variability (cycle-to-cycle or even device-to-device) of programmed resistance states is thus inevitable. Conversely, for artificial synapse applications in which the gradual resistance change can represent synaptic plasticity, analog switching, provided by gradual SET/RESET processes of interface-type RS is preferred, [3] as the Valence change memories, in which internal redox reactions control the change in resistance are promising candidates for resistive random access memories (ReRAMs) and neuromorphic computing elements. In this context, La 2 NiO 4+δ (L2NO4), a mixed ionic-electronic conducting oxide, well known for its highly mobile oxygen interstitial ions, emerges as a potential switching material for novel L2NO4-based memristive devices. However, their integration in complementary metal oxide semiconductor (CMOS) technology still has to be demonstrated, as the major focus of previous studies has been carried out on epitaxial films grown on single crystals. In this work, the optimization of the deposition temperature and precursor solution composition is presented, allowing to obtain high-quality polycrystalline L2NO4 thin films grown by metal organic chemical vapor deposition on a platinized silicon substrate, and to use these films to build memristive devices in vertical configuration with Ti top electrodes. A bipolar analog-type transition in resistance can be achieved in Ti/L2NO4/Pt memristive devices. While the "forming" process required for the devices based on nonoptimized L2NO4 thin films is considered as a drawback, the Ti/optimized L2NO4/Pt devices are formingfree and exhibit a good cyclability. These results prove the switching response of L2NO4-based devices in a vertical configuration for the first time.
www.advmattechnol.de number of stable and distinguishable resistance states is not limited by the abrupt set-event of filamentary switching.
Not only the switching layer but also the electrode material plays a significant role in the performance of VCMs. Indeed, by using oxidizable electrode materials, such as Ti, [14] Al, [15,16] and TiN, [17] the transport properties at the switching layer/electrode interface can be critically affected. For example, in Pt/ Ti/Pr 1-x Ca x MnO 3 (PCMO)/SrRuO 3 /SrTiO 3 and Ti/PCMO/Pt vertical heterostructures, the redox reaction occurring at the Ti electrode governs the RS, where the amount of fully oxidized Ti ions in the electrode determines the resistance state of the device. [18][19][20] It is widely accepted that the TiO x interlayer is spontaneously formed when Ti is evaporated on top of PCMO. Under positive bias applied at the active electrode, the accumulation of oxygen ions can cause further oxidation of the TiO x layer, leading to an added series resistance in the device and thus making it in HRS. The reverse process occurs when a negative voltage is applied and the LRS is achieved. This interlayer acts as an oxygen getter or oxygen reservoir and plays a key role in the memristive properties of the given device. [21][22][23] A vertical configuration is commonly used for memristors due to its reduced dimensions, compactness, and easiness for ReRAM devices fabrication, as well as compatibility for integration in cross-bar array architectures. [24] Nevertheless, given the small series resistance of the memristive layer, in particular for semiconducting oxides, which results from low film thickness (between a few nm to a few tens of nm), to avoid the device breakdown, the electrical current density should be carefully controlled by the current compliance.
In the last few years, there has been considerable research interest in the use of perovskite and perovskiterelated oxides, such as GdBaCo 2 O 5+δ , [25] GdBaCo 2 O 5+δ / LaNiO 3 , [26] LaNiO 3+δ , [17,27] La 2 NiO 4+δ , [28] Fe-doped SrTiO 3 , [29] La 1-x Sr x MnO 3-δ , [30] for VCM applications due to their highly tunable ionic and electronic transport properties, potentially allowing for multilevel resistance states. In this context, among the different materials proposed, La 2 NiO 4+δ (L2NO4) presents remarkable properties as an oxide switching layer for memristive devices, [23,28,31] including its mixed-ionic electronic conduction properties and its capability to accommodate a wide range of oxygen stoichiometry without decomposition. L2NO4 is the first member (n = 1) of the Ruddlesden-Popper (RP) La n+1 Ni n O 3n+1 series and can be described as the intergrowth of LaNiO 3 layers between individual LaO rock-salt type layers. Different from the majority of oxides used as memristive layers, in which oxygen vacancies are often the dopant defects, L2NO4 is chosen due to its oxygen storage capability and high oxygen mobility thanks to the oxygen interstitial point defects present in the structure. [32] We recently reported on the significant electroforming-free analog switching capabilities of epitaxial thin-film L2NO4-based devices grown on SrTiO 3 single-crystal substrate, both as single La 2 NiO 4+δ layer, [28] and as La 2 NiO 4+δ / LaNiO 3-δ bilayers. [31] Thus, combining L2NO4 with an oxidizable electrode opens the door to the development of new analog memristive devices with gradual SET and RESET processes, able to provide multilevel resistance states and suitable for mimicking synaptic behavior in neuromorphic computing. The single-layer planar devices, designed with an active Ti electrode and an inert Pt electrode (Ti/200 µm-L2NO4/Pt), showed gradual set and reset transitions and memory transience, suitable for artificial synapse applications. Furthermore, we also showed that the structural cell parameters, the orientation of the L2NO4 films in the bilayers, and the memristive properties of single-layer and bilayer devices could be tuned by varying the oxygen stoichiometry (δ) of the L2NO4 thin films through a post-anneal treatment [23] or changing the pO 2 of the deposition. [31] Remarkably, single-layer devices constructed using oxygen-rich L2NO4 films have a larger memory window and improved multilevel analog-type programming capabilities.
However, to integrate these promising memristors in real devices, the compact low-energy-consumption vertical configuration is greatly preferred. Therefore, a silicon-based structure, i.e., Pt/TiO 2 /SiO 2 /Si (hereafter referred to as Pt) was used in this work to integrate polycrystalline L2NO4 films into vertical memristive stacks. To grow high-quality L2NO4 films, we used the pulsed injection-metal organic chemical vapor deposition (PI-MOCVD) technique, as it enables to finely grow thin films over large areas with high uniformity and allows for a good control of the film thickness by controlling the number of injected microdroplets of precursor solution thanks to an electric injector valve. Moreover, the precursor solution can be simply prepared by dissolution of metal-organic precursors and the stoichiometry of the film is easily adjusted by varying their concentration. Classical MOCVD [33] and PI-MOCVD [34][35][36][37] have been previously used for the growth of epitaxial and polycrystalline L2NO4. However, to the best of our knowledge, the deposition of this layered structure had never been achieved by PI-MOCVD before on platinized silicon, substrates that suffer from dewetting when exposed at the typical high temperatures required for MOCVD deposition. This study focuses on the optimization of the deposition parameters to obtain homogenous, highly dense, phase pure and polycrystalline L2NO4 films, and on the building and testing of vertical L2NO4-based memristive devices for the first time.

Results and Discussion
Typically, high temperatures (≥650 °C) are usually required for the deposition of crystalline layered oxide structures, which experimentally lead to the dewetting of the Pt bottom electrode. In order to avoid this limitation, in this work, we explore the optimization of the deposition conditions in two steps: i) by decreasing the deposition temperature to find the best compromise to avoid the Pt dewetting while maintaining the crystallinity of the film, and ii) by varying the precursor solution composition to obtain stoichiometric, homogenous and highly dense L2NO4 films. The deposition conditions used for the two optimization series are detailed in Figure S1, Supporting Information. In the first step, the La/Ni ratio in the precursor solution (R) was fixed to 5.00, while the deposition temperature was varied from 650 °C to 600 °C, with a step of 25 °C. Second, the deposition temperature was fixed at 600 °C and R was varied from 5.00 to 4.00, with steps of 0.25.
In addition, to be embedded in realistic devices in the future, the fabrication process should be CMOS-BEOL (back-end-ofline) compatible where the temperature is required to be lower than 450 °C. To overcome this challenge, the deposition of www.advmattechnol.de amorphous L2NO4 thin film at 400 °C followed by a fast laser crystallization treatment [38][39][40] is considered as a promising approach. Another route to avoid heating above 450 °C would be to build amorphous L2NO4-based memristive devices. However, as the functional properties (electronic and ionic transport) of the amorphous films are expected to be different, their memristive properties might largely differ from the crystalline counterpart. The effects of the deposition temperature and solution composition on the growth of L2NO4 films will be discussed in the following sections.

Effect of the Temperature on the Growth of Polycrystalline L2NO4 Films
The influence of the deposition temperature on the film composition, crystallinity and morphology is assessed for deposition temperatures between 600 and 650 °C with a constant R of 5.00 (red dots in Figure 1). These samples La/Ni ratios, which increase with increasing deposition temperature, as shown in Figure 1a, were measured by the electron probe microanalysis (EPMA) technique. A clear linear relationship between these two parameters was obtained. The growth rates are 1.3 nm min -1 and 1.5 nm min -1 for depositions at 600 °C and 650 °C, which result in films of 43 ± 3 nm and 50 ± 3 nm by using 2000 pulses, respectively.
The grazing incidence X-ray diffraction (GI-XRD) patterns obtained for these three films are shown in Figure 1b. The Pt substrate peaks are indicated by gray dots. The main diffraction peaks observed are attributed to the L2NO4 tetragonal phase (space group I4/mmm, ICDD: 00-034-0314) in polycrystalline form (randomly oriented), with small peaks corresponding to the La 2 CO 5 phase. The intensity of the impurity phase decreases as the deposition temperature decreases, in agreement with the decrease of La/Ni ratio in the films (Figure 1a). Moreover, an amorphous thin film can be obtained by lowering the deposition down to 500 °C, while at 550 °C a mixture of the L2NO4 and La 3 Ni 2 O 7 phases is obtained, with a small contribution of the La 2 CO 5 phase (see Figure S2 in the Supporting Information).
The top-view scanning electron microscopy (SEM) images of films deposited at 650 °C, 625 °C, and 600 °C are shown in Figure 2a-c, respectively. Their surface morphology is quite similar, formed by randomly oriented grains with small grain sizes of the order of 25-45 nm. All films are homogeneous, polycrystalline, and dense. Moreover, no cracking nor pinholes were observed in any of the samples. It can be observed that the grain size is largest for the 650 °C deposition, and decreases for the lower deposition temperatures.
The corresponding atomic force microscopy (AFM) images of these L2NO4 samples can be found in Figure 2d-f. The sample deposited at 650 °C presents larger particle sizes (root-mean-square (RMS) of 42.1 nm), compared to the films deposited at lower temperatures. At this temperature the small grains cluster to form larger ones, resulting in a film with a larger roughness. At lower temperatures, the size of the individual particles is similar (RMS of 23.4-24.0 nm), and smaller than that observed for the sample grown at 650 °C, in agreement with the SEM observations. The L2NO4 films deposited at 625 °C and 600 °C are flatter, as measured by the RMS surface roughness, which decreases from 6.6 to 3.4 nm when the temperature is reduced from 650 °C to 600 °C (see Table 1). The higher roughness of the L2NO4 film deposited at 650 °C can be explained by the L2NO4 grain coarsening and by the evolution of Pt grains during the deposition under a relatively high temperature. The improvement (decrease) of surface roughness when decreasing the deposition temperature is also confirmed by the scanning transmission electron microscopy (STEM) cross-sectional images of L2NO4 films deposited at 600 °C ( Figure 4a) and at 650 °C ( Figure S4, Supporting Information)

Effect of the Solution Composition on the Growth of Polycrystalline L2NO4 Films
Due to the smaller film roughness and flatter surface, 600 °C was selected as deposition temperature to grow the L2NO4 films. However, under these deposition conditions, the films present the secondary La 2 CO 5 phase (red diffractogram,  www.advmattechnol.de Figure 1b). In order to improve the film purity at this temperature, several films were prepared by varying the R value from 4.00 to 5.00 (blue dots in Figure S1, Supporting Information). The La/Ni ratios obtained by EPMA for these thin film samples, together with their GI-XRD patterns of are shown in Figure 3a,b, respectively. By reducing R from 5.00 to 4.50, it is possible to eliminate the presence of impurities, which is confirmed by the absence of the La 2 CO 5 peaks. Thus, only the reflections of the L2NO4 tetragonal phase are observed in the films deposited at 600 °C using R values of 4.25 and 4.00. However, only the film deposited at the R of 4.00 in the source gives a ratio of 1.95 in the L2NO4 film, which is close to the desired value of 2 for the highly pure L2NO4 phase. Therefore, the optimized conditions which allowed preparing high-quality polycrystalline and flat L2NO4 films on Pt, without dewetting are: deposition temperature of 600 °C and R of 4.00. These deposition conditions were selected for the film growth and subsequent vertical memristive device fabrication.
In terms of morphology, by decreasing the R value, no major difference is observed, as shown in the SEM images of those samples, displayed in Figure S3a-d, Supporting Information.
The optimized film (i.e., deposition temperature at 600 °C with R of 4.00) was then used to construct the L2NO4-based memristive devices. SEM and AFM top-view images of the optimized film are shown in Figure 3c,d, respectively. The morphology observed by SEM is similar to that of the film grown at 600 °C with R of 5.00 (shown in Figure 2c), suggesting that the La/Ni ratio in the precursor solution does not have an effect on the morphology of the film. An RMS value of 2.8 nm and an average grain size of 23.7 nm are calculated from the AFM measurements, which are in agreement with those reported for the films deposited at 600 °C (Table 1).  www.advmattechnol.de

Microstructural Characterization of the Ti/L2NO4/Pt Memristive Devices in Vertical Configuration
To build the memristive devices, electrodes consisting of 25 nm of Ti covered by 75 nm of Pt, were evaporated on top of the optimized L2NO4 film. In order to study the quality of the device heterostructure, a lamella across the whole stack (from the Pt layer of the top electrode to the SiO 2 layer of the substrate) was prepared by focused ion beam (FIB) milling and the STEM image of the lamella is shown in Figure 4a. Continuous dense Ti and Pt layers on top of the L2NO4 thin film can be observed, with sharp L2NO4/Ti and Ti/ Pt interfaces, and without dewetting nor Pt diffusion. The grains of the L2NO4 layer increase in size with increasing film thickness (V-shaped grains, as indicated by the red dashed line in Figure 4a). Therefore, as can be observed in the image, the number of grains per 100 nm in-plane length decreases from approximately 6-8 grains at bottom part to 4-5 grains at top region. The size of the top grains is thus in good agreement with the AFM results (i.e., 23.7 nm) shown in Figure 3d. Besides, 1 to 2 grains of varying length can be measured along the surface normal direction within 43-nm thick L2NO4 layer. The chemical composition of the lamella was characterized by energy-dispersive X-ray spectroscopy (EDX), as shown by the EDX atomic depth profile ( Figure 4b) and EDX maps (Figure 4c) of the lamella cross-section. These results show, from top to bottom, a clearly delimited Pt capping layer, a continuous Ti top electrode, the L2NO4 memristive oxide layer and the Pt bottom electrode, with sharp interfaces between the layers of the heterostructure and a uniform La and Ni composition within the L2NO4 film thickness. In addition, the presence of oxygen within the Ti layer can be detected. This observation suggests the spontaneous formation of a TiO x interlayer when the Ti electrode is put in contact with the L2NO4 film.

Memristive Characteristics of the Ti/L2NO4/Pt Devices in Vertical Configuration
To study the RS behavior of the Ti/optimized L2NO4/Pt devices, beforehand the initial resistance states (IRS) were measured giving an average value of 434 Ω for the 20 2 µm 2 devices. The I-V characteristics were recorded by applying symmetric bipolar voltage sweeps (0 V → +V max → 0 V → -V max → 0 V). The HRS and LRS were read at +0.01 V after each halfsweep. First, an initialization process consisting of DC sweeps of increasing voltage amplitude (Figure 5a-d, plotted as R-V curves) was carried out to increase the Ti/L2NO4/Pt device to a higher resistance state. Then the device operates at ±3 V, as shown in Figure 5e (R-V plot). The first three sweeps between ±1 V show nonlinear and rectifying electrical properties (see Figure 5a) with a resistance of 1 kΩ (read at low voltage). Figure 5b shows that the resistance increases during the next three sweeps at |V max | = 2 V and a small hysteresis starts to appear, however, the two resistance states are not clearly distinguishable. A larger hysteresis with two noticeably different states is obtained for the Ti/L2NO4/Pt device when cycled between ±2.5 V (Figure 5c). Figure 5d,e shows continuous R-V

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curves with gradual transitions between resistance states at |V max | = 2.75 V and |V max | = 3 V, respectively, with a HRS/LRS ratio of around 11 for both working voltages. Thus it can be concluded that the Ti/optimized L2NO4/Pt devices can operate using |V max | in the range of 2.5-3 V. In all cases, the reset process takes place at positive voltages and the set process at negative voltages. A continuous gradual change in resistance during both the SET and RESET processes is observed, without any abrupt jumps, which is considered as a prerequisite of analogtype device operation. The observed RS is also compatible with a valence change mechanism taking place at the L2NO4/Ti interface. By the application of a positive voltage to the Ti electrode, the drift of oxygen ions would induce the further oxidation of the TiO x interlayer, and the concomitant resistance increase. This oxidation would be reversed by the application of a negative voltage, leading to the reduction of the TiO x interlayer and reoxidation of the L2NO4 film. In addition, these results are in good agreement with the gradual memristive behavior previously obtained on Pt/(epitaxial) L2NO4/Ti planar devices, [23,28] which has now been successfully reproduced in vertical configuration for reduced dimensions devices and using lower operation voltages.
To verify the interfacial switching observed on Ti/optimized L2NO4/Pt devices, the electrode area dependence test was carried out. The HRS and LRS states were read at 10 mV after +3 V sweep and -3 V sweep, respectively, for different electrode sizes (i.e., 20 2 µm 2 , 50 2 µm 2 , 100 2 µm 2 ). Three devices were measured for each pad size, except for the 100 2 µm 2 electrode, for which only one device was measured because most of the 100 2 µm 2 devices suffered a breakdown at this operation voltage. This is most likely due to the presence of a leakage current resulting from the presence of larger amount of defects in the larger devices, as often observed in the literature for other materials. [41] The average value of the HRS and LRS are plotted as a function of contact area in Figure 5f. This plot shows a clear decrease in HRS and LRS when increasing the pad size. The slopes are -1.66 and -1.05 for the HRS and LRS, respectively. These results suggest that the change would not be limited to a single filament, but most probably takes place over the entire electrode area and, thus, the Ti/optimized L2NO4/Pt memristors present interface-type RS.
To compare the switching properties of memristive devices based on non-optimized L2NO4 films and the previously shown results on the optimized L2NO4 films, beforehand the IRS of the 20 2 µm 2 devices was measured giving the average value of 48.8 kΩ. Then, standard IV sweeps with different |V max | were carried out on the Ti/non-optimized L2NO4/Pt devices. Figure 6a presents the nonlinear electrical properties with a resistance of roughly 87 kΩ. Next, sweeps at ±2, ±2.5, ±2.75, ±3 V were carried out. The sweeps at ±3 V are displayed (Figure 6b) in this article showing that, by increasing the |V max |, the device resistance decreases. In the positive branch, the hysteresis starts to appear with eight wise switching sense. An abrupt change in resistance to lower values, hereafter referred to as "forming" step, can be observed during the ±3.25 V sweep, as indicated in Figure 6c. After the "forming," the device can operate at a lower working voltage range (|V max | = 2.75 V) as shown in Figure 6d, with a HRS/LRS ratio of 6 in this case. We propose that, the much higher IRS measured for the nonoptimized L2NO4  www.advmattechnol.de devices compared to the optimized L2NO4 devices (48.8 kΩ vs 434 Ω, respectively) could be due to the presence of the La 2 CO 5 impurity phase observed by XRD, and that the abrupt resistance change could be due to the breakdown of this impurity blocking layer, reaching then the standard operation cycles of the optimized L2NO4-based devices. It should be noted that this process is not the classical electroforming occurring in filamentary VCMs, where a conducting filament is created within the switching layer.
In order to study the RS performance, another 20 2 µm 2 Ti/ optimized L2NO4/Pt memristor was selected to test the data retention and the endurance. Figure 7a shows the retention of the device measured after an initialization process followed by 5 cycles at ±2.5 V. A decrease of the HRS from 43.4 to 24.2 kΩ (56%) and an increase of LRS from 5.9 to 10.0 kΩ (169%) are observed after 12 h. The dynamic resistance relaxation of the HRS was previously observed in Ti/200 µm-L2NO4/Pt devices and is attributed to the oxygen mass transport between p-type L2NO4 and n-type TiO x . [28] Figure 7b shows the resistances (read at 0.01 V after ±2.5 V sweep) as a function of the number of sweeps (500 consecutive sweeps) showing no overlap of the HRS and LRS states.

Conclusions
Optimized flat and dense polycrystalline L2NO4 thin films (43 nm thick) have been deposited by PI-MOCVD on a platinized silicon substrate by, after an optimization process in which the deposition temperature and the La/Ni atomic ratio of the precursor solution were tuned. The purity of the L2NO4 phase in thin film was confirmed by XRD and by the La/Ni ratio close to 2 measured using the EPMA technique. Ti/L2NO4/Pt memristive devices have been fabricated in vertical configuration for the first time, using L2NO4 thin films deposited under the previously optimized conditions. A TiO x interlayer was observed by STEM-EDX analysis when evaporating Ti on top of the L2NO4 memristive film. The Ti/L2NO4/ Pt devices present gradual transitions between the HRS and LRS states, suggesting bipolar analogue RS can be obtained.  In addition, the Ti/optimized L2NO4/Pt memristive devices are forming-free with dynamic resistance relaxation during 12 hours and good cyclability; whereas the Ti/non-optimized L2NO4/Pt devices have a higher initial resistance and require a "forming" step before exhibiting similar RS characteristics to the optimized ones. This work constitutes the first proof of the successful integration of vertical L2NO4-based memristors on silicon-based substrates and allows for the future development of these promising redox-based memristive devices in applications such as artificial synapses for neuromorphic computing with bio-inspired learning
Instrumentation: To identify the phase and evaluate the structural crystal quality of the samples, X-ray diffraction was performed in a 5-circle Rigaku Smartlab diffractometer. GI-XRD was used to enhance the diffraction signal from the polycrystalline films and minimize the signal of the silicon-based substrates. The study of surface morphology was carried out by SEM in a SEM FEG ZEISS GeminiSEM 300. To investigate the film roughness, AFM images were performed using a AFM D3100 Veeco Instrument in tapping mode with a Si 3 N 4 tip probe. The chemical film composition was analyzed by EPMA using a CAMECA SX100 spectrometer. Each film was measured at two different acceleration voltages: 12 keV and 16 keV and the data analysis was done by Strategem software. The TEM-EDX analyses were performed at 200 kV using a probe corrected Tecnai Osiris FEI microscope equipped with the Super-X detector system. Prior to the TEM examination, the sample was prepared by FIB milling using a FEI dual-beam Helios 450S. The lamella was covered by a platinum layer to ensure surface protection from the tails of the ion beam. A 30 kV operation voltage was used for the rough milling and then a reduction in the range 2-8 kV to limit the surface damages. Finally, the sample was cleaned with a very soft oxygen-argon plasma to remove surface hydrocarbon contamination, process from which no ion implantation is expected.
The device fabrication was carried out in clean-room facilities (PTA, Grenoble), including metal evaporation (Plassys MEB550) using laser lithography (Heidelberg instrument µPG 101). Metal electrodes were then patterned (by laser lithography) and evaporated on top of the L2NO4 thin films, i.e., 25 nm of Ti followed by 75 nm of Pt (Ti acts as the active electrode, covered by capping Pt layer in order to protect Ti from oxidation with the atmosphere).
The electrical measurements (triangular voltage sweeps) were performed under ambient conditions using a source-measurement unit (Keithley 4200 semiconductor parameter analyzer) and two external micromanipulators. For all the I-V plots shown in this work, the voltage was applied on the Pt/Ti electrode while the Pt bottom electrode was grounded. The bipolar triangular voltage sweeps always start from zero bias and follow this sense: 0 V → +V max → 0 V → -V max → 0 V. The resistance state (HRS and LRS) was read by applying a reading test 0 V → +0.01 V and measuring the corresponding current at 0.01 V after an individual half sweep: 0 V → +V max → 0 V or 0 V → -V max → 0 V.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.