A single-source C++20 HLS flow for function evaluation on FPGA and beyond

Luc Forget (1) , Gauthier Harnisch (1) , Ronan Keryell (1) , Florent de Dinechin (2)

1 AECG - Adaptive and Embedded Computing Group
2 EMERAUDE - Systèmes Embarqués audio programmables

This paper presents a framework to reuse the intelligence of RTL generators in a single-source HLS setting. This framework is illustrated by a C++ fixed-point library to generate mathematical function evaluator. A compiler flow from C++20 to Vivado IPs has been developed to make the library usable with Vitis HLS. This flow is demonstrated on two applications: an adder for the logarithmic number system, and additive sound synthesis. These experiments show that the approach allows to easily tune the precision of the types used in the application. They also demonstrate the ability to generate arbitrary function evaluator at the required precision.

Domaines: Arithmétique des ordinateurs

Luc Forget, Gauthier Harnisch, Ronan Keryell, Florent de Dinechin. A single-source C++20 HLS flow for function evaluation on FPGA and beyond. HEART 2022 - 12th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Jun 2022, Tsukuba, Japan. ⟨hal-03684757⟩