Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology

Y. Rey-Tauriac (1) , J. Badoc (1) , B. Reynard (1) , R.A. Bianchi (1) , D. Lachenal (2, 1) , Alain Bravaix (3, 2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 Yncréa Méditerrané

This paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, Vds limited and Vgs limited applications in order to improve circuit designs. For Vds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carrier injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor.

Mots clés: N-Drift; CMOS; Safe Operating Area (SOA)

Domaines: Sciences de l'ingénieur [physics]

Y. Rey-Tauriac, J. Badoc, B. Reynard, R.A. Bianchi, D. Lachenal, et al.. Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology. Microelectronics Reliability, 2005, 45 (9-11), pp.1349-1354. ⟨10.1016/j.microrel.2005.07.019⟩. ⟨hal-03661057⟩