Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Bruno Neckel Wesling (1) , Marina Deng (1) , Mukherjee Chhandak (1) , Magali de Matos (1) , Abhishek Kumar (2) , Guilhem Larrieu (2) , Jens Trommer (3) , Thomas Mikolajick (3) , Cristell Maneux (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique
3 NaMLab gGmbH

In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic smallsignal parameters such as the gate capacitances.

Mots clés: Test structure; Equivalent circuit; Parasitic components; RF measurements; De-embedding

Domaines: Micro et nanotechnologies/Microélectronique

Bruno Neckel Wesling, Marina Deng, Mukherjee Chhandak, Magali de Matos, Abhishek Kumar, et al.. Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor. Solid-State Electronics, 2022, 194, pp.108359. ⟨10.1016/j.sse.2022.108359⟩. ⟨hal-03657781⟩