A novel Network-on-Chip security algorithm for tolerating Byzantine faults

Soultana Ellinidou (1) , Gaurav Sharma (1) , Olivier Markowitch (1) , Jean-Michel Dricot (1) , Guy Gogniat (2)

1 ULB - Université libre de Bruxelles
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Since the number of processors and cores on a single chip is increasing, the interconnection among them becomes significant. Network-on-Chip (NoC) has direct access to all resources and information within a System-on-Chip (SoC), rendering it appealing to attackers. Malicious attacks targeting NoC are a major cause of performance depletion and they can cause arbitrary behavior of links or routers, that is, Byzantine faults. Byzantine faults have been thoroughly investigated in the context of Distributed systems however not in Very Large Scale Integration (VLSI) systems. Hence, in this paper we propose a novel fault model followed by the design and implementation of lightweight algorithms, based on Software Defined Network-on-Chip (SDNoC) architecture. The proposed algorithms can be used to build highly available NoCs and can tolerate Byzantine faults. Additionally, a set of different scenarios has been simulated and the results demonstrate that by using the proposed algorithms the packet loss decreases between 65% and 76% under Transpose traffic, 67% and 77% under BitReverse and 55% and 66% under Uniform traffic.

Mots clés: Byzantine Faults; BFT; Network-on-Chip; NoC

Domaines: Architectures Matérielles [cs.AR]

Soultana Ellinidou, Gaurav Sharma, Olivier Markowitch, Jean-Michel Dricot, Guy Gogniat. A novel Network-on-Chip security algorithm for tolerating Byzantine faults. 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati, Italy. pp.1-6, ⟨10.1109/DFT50435.2020.9250906⟩. ⟨hal-03606356⟩