Morphology and reliability aspects of 40 nm eSTM™ architecture

Franck Melul (1, 2) , V. Della Marca (1) , Marc Bocquet (1) , Madjid Akbal (2) , Pierre Laine (1) , Frederique Trenteseaux (3) , Marc Mantelli (2) , Marjorie Hesse (2) , Arnaud Regnier (2) , Stephan Niel (3) , Francesco Rosa (2)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 ST-ROUSSET - STMicroelectronics [Rousset]
3 ST-CROLLES - STMicroelectronics [Crolles]

In this paper, we present an experimental study of a new architecture of the embedded Select in Trench Memory (eSTM™) cell. A first part is dedicated to a deep analysis of the overlap eSTM TM behaviour. A key fact is the possibility to achieve a large programming window thanks to tip effect enhanced erase. After the study on erase operation scheme, we demonstrate the impact of Select to Floating gate tip coupling on the endurance results. The endurance results are thus improved up to 500k cycles using the overlap eSTM TM .

Mots clés: Floating gate memory; Split-gate memory; Endurance degradation; NVM; Reliability

Domaines: Micro et nanotechnologies/Microélectronique

Franck Melul, V. Della Marca, Marc Bocquet, Madjid Akbal, Pierre Laine, et al.. Morphology and reliability aspects of 40 nm eSTM™ architecture. Microelectronics Reliability, 2021, 126, pp.114266. ⟨10.1016/j.microrel.2021.114266⟩. ⟨hal-03596892⟩