Modeling transistor level masking of soft errors in combinational circuits

Ihsen Alouani (1, 2) , Smail Niar (3) , Yassin El Hillali (1, 2) , Atika Rivenq (1, 2)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 COMNUM - IEMN - COMmunications NUMériques - IEMN
3 LAMIH - Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201

Technology scaling in modern electronic circuits shrinks the transistor size and dramatically increases the sensitivity of semiconductor devices to radiations. Consequently, soft errors emerged as a serious reliability threat in both sequential and combinational circuits. To accurately estimate Soft Error Rates (SERs) within combinational circuits, the impact of masking mechanisms should be considered and precisely modeled. In fact, overestimating SERs may lead to unnecessary hardware resources overhead as well as higher power consumption and circuit complexity. This paper examines the effect of logic gates architecture on the SERs in CMOS logic circuits. We consider the impact of the Transistor Level Masking (TLM) and propose a probabilistic model for both circuit and gate levels The experimentations show that the probability of soft error masking due to TLM mechanism can reach 100% for NAND gates, 45% for c17 ISCAS'85 benchmark and 47% for a simplified c6288 ISCAS'85 benchmark. © 2015 IEEE.

Mots clés: Semiconductor devices; Transistors; Circuit complexity; CMOS logic circuits; Hardware resources; Probabilistic modeling; Soft error masking; Technology scaling; Transistor level; Transistor size; Computer circuits; Error correction; Errors; Radiation hardening; Reconfigurable hardware

Domaines: Sciences de l'ingénieur [physics]

Ihsen Alouani, Smail Niar, Yassin El Hillali, Atika Rivenq. Modeling transistor level masking of soft errors in combinational circuits. 2015 IEEE East-West Design and Test Symposium, EWDTS 2015, Sep 2015, Batumi, United States. pp.7493140, ⟨10.1109/EWDTS.2015.7493140⟩. ⟨hal-03528693⟩