Memristor models optimization for large-scale 1T1R memory arrays

Basma Hajri (1) , Mohammad M Mansour (2) , Ali Chehab (3) , Hassen Aziza (1)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 AUB - American University of Beirut Faculty of Medicine and Medical Center
3 AUB - American University of Beirut [Beyrouth]

Recently, memristive devices have been shown to possess unique and intriguing properties such as small size, high density, non-volatility, state-dependent behavior, good scalability, very low leakage current, and compatibility with CMOS technology. A critical requirement for using memristive devices at the circuit level is the availability of a simple, accurate and efficient model that adequately characterizes circuit performance. Most existing models for memristive devices presented in the literature suffer from high complexity and computational inefficiency. In this paper, we propose a new scheme to reduce the complexity of existing models and improve simulation time while maintaining circuit designer requirements in terms of accuracy. Using this technique, the simulation time can be improved by around 20% while maintaining a good accuracy.

Mots clés: Memristor; models; complexity reduction; Resistive Random Access Memory (RRAM); simulation time; model optimization

Domaines: Micro et nanotechnologies/Microélectronique

Basma Hajri, Mohammad M Mansour, Ali Chehab, Hassen Aziza. Memristor models optimization for large-scale 1T1R memory arrays. 2018 International Conference on IC Design & Technology (ICICDT), Jun 2018, Otranto, France. pp.109-112, ⟨10.1109/ICICDT.2018.8399768⟩. ⟨hal-03526089⟩