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Reusable System-level Power-aware IP Modeling Approach

Abstract : In many areas of the semiconductor industry, System-on Chip (SoC) power analysis and management is a critical process for maintaining low-power profiles. Due to the complexity of modern SoC designs and the definition of their power management strategies, it is common to reuse available resources such as Intellectual Properties (IP) and power intent descriptions in the Unified Power Format (UPF). However, this is typically initiated at the Register Transfer Level (RTL) and beyond. In this study, we provide a new, earlier approach to enable system-level power intent definition and power management strategy description around IPs or entire SoCs. This approach follows UPF semantics and allows for the creation of reusable, power-aware IP models. In addition, it adds a description of clock intent into this model and simplifies the separation of designs into clock domains and the application of dynamic power reduction techniques. The approach is built around the PwClkARCH power modeling and estimation tool and its capabilities are demonstrated using an example of reusing power-aware SystemC-TLM IP models from NXP’s i.MX8 SoC series.
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Contributor : sophie gaffé-clément Connect in order to contact the contributor
Submitted on : Monday, November 29, 2021 - 9:13:54 AM
Last modification on : Thursday, August 4, 2022 - 4:56:51 PM


  • HAL Id : hal-03454118, version 1



Antonio Genov, François Verdier, Loic Leconte. Reusable System-level Power-aware IP Modeling Approach. Design and Verification DVCon U.S. 2022, accellera, Feb 2022, conférence virtuelle (initialement prévue à San Jose), United States. pp.10. ⟨hal-03454118⟩



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