Formal Verification for Validation of PSEEL's PLC Program

Mohamed Niang (1) , Philippot Alexandre (1) , François Gellot (1) , Raphaël Coupat (1) , Bernard Riera (1) , Sébastien Lefebvre (2)

1 CRESTIC - Centre de Recherche en Sciences et Technologies de l'Information et de la Communication - EA 3804
2 IFSTTAR/LEOST - Laboratoire Électronique Ondes et Signaux pour les Transports

In order to keep its leadership in French rail market and to improve work conditions of its systems engineers during automation projects, the SNCF (French acronym for National Society of French Railways) wants to develop solutions increasing the productivity. One of these improvements focuses on the current methodology used by systems engineers to verify and validate PLC programs of electrical installations. This task remains one of the most important during an automation project because it is supposed to ensure installations safety, but it must be optimized. Through an industrial thesis financed by SNCF, the aim of this research project is to improve this method and reduce time validation of programs by providing a tool which will help systems engineers to verify and validate quickly and automatically PLC programs during any automation project, not necessarily during factory tests but directly from their office.

Mots clés: Model-checking; recipe book; factory tests; systems engineers; railways; safety

Domaines: Automatique / Robotique

Mohamed Niang, Philippot Alexandre, François Gellot, Raphaël Coupat, Bernard Riera, et al.. Formal Verification for Validation of PSEEL's PLC Program. 14th International Conference on Informatics in Control, Automation and Robotics (ICINCO), Jul 2017, Madrid, Spain. ⟨hal-03427253⟩