Heterogeneous multicore SDRAM interference analysis

Alfonso Mascareñas González (1) , Frédéric Boniol (2) , Youcef Bouchebaba (2) , Jean-Loup Bussenot (2) , Jean-Baptiste Chaudron (1)

1 DISC - Département d'Ingénierie des Systèmes Complexes
2 DTIS, ONERA, Université de Toulouse [Toulouse]

The purpose of this paper is to describe a set of DDR3 SDRAM interference estimation cost functions. The arbitration system of the SDRAM controller heavily impact the interference analysis. In this work, three arbitration are considered, corresponding to the situations where the accessed memory address belongs to the same block address, different memory banks and different rows. The aim of these functions is to estimate the instructions interference overhead may suffer when concurrently accessing these three logical addresses in a SDRAM saturation context. To develop these interference expressions, specific measurement systems, micro-benchmarks and theory on SDRAM controllers have been used.

Mots clés: Multicore; DDR3 SDRAM Controller; WCET; Cost functions

Domaines: Autre

Alfonso Mascareñas González, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot, Jean-Baptiste Chaudron. Heterogeneous multicore SDRAM interference analysis. The 29th International Conference on Real-Time Networks and Systems (RTNS '21), Apr 2021, Virtual event, France. pp.12-23. ⟨hal-03383504⟩