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Introducing 3-nm Nano-Sheet FET technology in Microwind

Abstract : This paper describes the implementation of the novel Nano-sheet FET (NS-FET) for the 3-nm CMOS technology node in Microwind. After a general presentation of the electronic market and the roadmap to the atomic scale, design rules and basic metrics for the 3-nm node are presented. Concepts related to the design of NS-FET and design for manufacturing are also described. The performances of a ring oscillator, basic cells, sequential cells and a 6-transistor RAM memory are also analyzed.
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Contributor : Etienne Sicard Connect in order to contact the contributor
Submitted on : Thursday, October 14, 2021 - 11:15:29 AM
Last modification on : Friday, October 29, 2021 - 3:56:21 AM


App note 3nm -v7.pdf
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  • HAL Id : hal-03377556, version 1


Etienne Sicard, Lionel Trojman. Introducing 3-nm Nano-Sheet FET technology in Microwind. 2021. ⟨hal-03377556⟩



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