Skip to Main content Skip to Navigation
New interface
Conference papers

Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level

Quentin Forcioli 1, 2, 3, 4 Jean-Luc Danger 2, 3, 4, 1 Clémentine Maurice 5 Lilian Bossuet 6 Florent Bruguier 7 Maria Mushtaq 7 David Novo 7 Loïc France 7 Pascal Benoit 7 Sylvain Guilley 8, 2, 3, 4 Thomas Perianin 8 
4 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
5 SPIRALS - Self-adaptation for distributed services and large software systems
Inria Lille - Nord Europe, CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189
7 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information. Indeed, the increase in complexity of modern CPU and SoC is mainly driven by the seek of performance rather than security. Even if efforts like isolation techniques have been taken to thwart cyberattacks, most microarchitectural features can open the door to security holes. One typical example is the exploitation of cache memory which keeps track of the program execution and paves the way to side-channel (SCA) analysis and transient execution attacks like Meltdown and Spectre, which take advantage of speculative execution. This paper introduces an ongoing study aiming at analyzing the attacks relying on the hardware vulnerabilities of the microarchitectures of CPUs and SoCs. The main objective is to create a virtual and open platform that simulates the behavior of microarchitectural features and their interactions with the peripherals, like accelerators and memories in emerging technologies. The gem5 simulator, whose configuration can be customized to a specific CPU or SoC architecture, is the basis of our chosen platform for security analysis.
Document type :
Conference papers
Complete list of metadata

https://hal.archives-ouvertes.fr/hal-03353878
Contributor : Lilian Bossuet Connect in order to contact the contributor
Submitted on : Tuesday, September 28, 2021 - 4:57:54 PM
Last modification on : Tuesday, November 22, 2022 - 2:26:16 PM
Long-term archiving on: : Wednesday, December 29, 2021 - 7:03:06 PM

File

silm21_forcioli.pdf
Files produced by the author(s)

Identifiers

Citation

Quentin Forcioli, Jean-Luc Danger, Clémentine Maurice, Lilian Bossuet, Florent Bruguier, et al.. Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level. EuroS&PW 2021 - IEEE European Symposium on Security and Privacy Workshops, Sep 2021, Vienne, Austria. pp.96-102, ⟨10.1109/EuroSPW54576.2021.00017⟩. ⟨hal-03353878⟩

Share

Metrics

Record views

146

Files downloads

227