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FPGA Acceleration of the Horn and Schunck Hierarchical algorithm

Abstract : This work proposes a highly tunable motion estimation architecture. We implement the Horn and Schunck algorithm with the hierarchical extension for larger motion estimations in FPGAs. Different architectures are explored dealing with interpolation, pipeline, parallelism and arithmetic format, in order to fit performance. We show in our exploration, how the different cores of our system should be used to increase the throughput. Our smallest design achieves a 30.8 Mpixel/s in a 1024×1024 resolution and the fastest 507 Mpixel/s which is one of the fastest ever achieved, as far as we know, for FPGAs.
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Contributor : Lionel Lacassagne Connect in order to contact the contributor
Submitted on : Wednesday, September 1, 2021 - 11:34:53 AM
Last modification on : Sunday, June 26, 2022 - 3:12:46 AM
Long-term archiving on: : Thursday, December 2, 2021 - 6:52:26 PM


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Ilias Bournias, Roselyne Chotin, Lionel Lacassagne. FPGA Acceleration of the Horn and Schunck Hierarchical algorithm. International Symposium on Circuits and Systems (ISCAS), May 2021, Daegu, South Korea. ⟨10.1109/ISCAS51556.2021.9401068⟩. ⟨hal-03330803⟩



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