Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part I

Julien Borrel (1) , Louis Hutin (2) , Olivier Rozeau (2) , Marie-Anne Jaud (2) , Sebastien Martinie (1) , Magali Gregoire (1) , Emmanuel Dubois (3) , Maud Vinet (1)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 MICROELEC SI - IEMN - Microélectronique Silicium - IEMN

Aiming at overcoming the Fermi-level pinning (FLP) occurring at the metal/semiconductor interfaces, metal/insulator/semiconductor (MIS) contacts to n-Si and p-Si are usually treated in separate optimization studies, yet with no particular insight on their technological compatibility. In this paper, using 1-D analytical modeling of MIS contacts, it is shown that in order to fully benefit from FLP mitigation on both n- and p-type Si, a single-insertion/single-metallization scheme cannot be considered. In addition, it is demonstrated that associating given numerical values of contact resistivity with MIS contacts results in a thorny problem, since their I-V characteristics are nonsymmetric nonlinear.

Mots clés: 1-D modeling; CMOS; metal/insulator/semiconductor (MIS) contacts; nFET and pFET cointegration; T-WKB approximation; metal/insulator/ semiconductor (MIS) contacts; T WKB approximation

Domaines: Micro et nanotechnologies/Microélectronique

Julien Borrel, Louis Hutin, Olivier Rozeau, Marie-Anne Jaud, Sebastien Martinie, et al.. Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part I. IEEE Transactions on Electron Devices, 2016, 63 (9), pp.3413-3418. ⟨10.1109/TED.2016.2590836⟩. ⟨hal-03325007⟩