Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part II

Julien Borrel (1) , Louis Hutin (2) , Olivier Rozeau (2) , Marie-Anne Jaud (2) , Sebastien Martinie (2) , Magali Gregoire (1) , Emmanuel Dubois (3) , Maud Vinet (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 MICROELEC SI - IEMN - Microélectronique Silicium - IEMN

In this paper, the insertions of dielectric in metal/insulator/semiconductor contacts are considered via their associated impact on the dc and ac performances. Based on dc output characteristics projections, we found that single insertion and/or single-metal integration schemes are unlikely to result in simultaneously successful Fermi-level pinning alleviation on both n and pFETs. We show that the added C-MIS contributes to a significant extra improvement in terms of intrinsic inverter delay. In particular, an optimal configuration consisting of Pt-liner/p-Si and Zr/TiO2( 15 angstrom)/n-Si contacts can lead to a ring oscillator frequency higher than that of p and nFETs each flanked by ideal ohmic contacts with 10(-9) Omega.cm(2) resistivity.

Mots clés: Metal/insulator/semiconductor (MIS) contacts; n and pFETs cointegration; ring oscillators (ROs) frequency

Domaines: Micro et nanotechnologies/Microélectronique

Julien Borrel, Louis Hutin, Olivier Rozeau, Marie-Anne Jaud, Sebastien Martinie, et al.. Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part II. IEEE Transactions on Electron Devices, 2016, 63 (9), pp.3419-3423. ⟨10.1109/TED.2016.2590826⟩. ⟨hal-03325006⟩