Skip to Main content Skip to Navigation
Other publications

Introducing 20 nm technology in Microwind

Abstract : This paper describes the implementation of the CMOS 20 nm technology of a High Performance Bulk Planar 20nm CMOS Technology proposed by the Joint Development Alliance (JDA) in Microwind38. Power, performance and area (PPA) gains related to the 20 nm technology are illustrated, and new concepts such as design for manufacturing, double-patterning, replacement metal gate process are described. The performances of a ring oscillator layout and a 6-transistor RAM memory layout are also analyzed.
Document type :
Other publications
Complete list of metadata

https://hal.archives-ouvertes.fr/hal-03324322
Contributor : Etienne Sicard Connect in order to contact the contributor
Submitted on : Monday, August 23, 2021 - 3:02:36 PM
Last modification on : Tuesday, October 19, 2021 - 11:17:37 PM
Long-term archiving on: : Wednesday, November 24, 2021 - 6:39:19 PM

File

Application_Note_mw38_20nm_v7-...
Files produced by the author(s)

Identifiers

  • HAL Id : hal-03324322, version 1

Citation

Etienne Sicard. Introducing 20 nm technology in Microwind. 2011. ⟨hal-03324322⟩

Share

Metrics

Record views

20

Files downloads

26