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Introducing 65 nm technology in Microwind3

Abstract : This paper describes the improvements related to the CMOS 65 nm technologies and the implementation of this technology in Microwind3. The main novelties related to the 65 nm technology such as enhanced strained silicon, process options and low-K dielectrics are described. The performances of a ring oscillator and the 6-transistor static memory layout are also analyzed.
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https://hal.archives-ouvertes.fr/hal-03324309
Contributor : Etienne Sicard Connect in order to contact the contributor
Submitted on : Monday, August 23, 2021 - 2:55:44 PM
Last modification on : Tuesday, October 19, 2021 - 11:17:37 PM
Long-term archiving on: : Wednesday, November 24, 2021 - 6:38:19 PM

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  • HAL Id : hal-03324309, version 1

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Etienne Sicard, Syed Aziz. Introducing 65 nm technology in Microwind3. 2011. ⟨hal-03324309⟩

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