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Towards Agile Hardware Designs with Chisel: a Network Use-case

Jean Bruant 1, 2 Pierre-Henri Horrein 1 Olivier Muller 2 Tristan Groleat 1 Frédéric Pétrot 2 
2 SLS - System Level Synthesis
TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
Abstract : Facing Distributed Denial-of-Service (DDoS) attacks that are growing in both number and intensity, cloud service providers' network stability is at stake. Mitigation systems must provide highly responsive lines of defense while handling terabits per second. Combining reconfigurability with guaranteed throughput and latency, FPGAs are recognized targets for high-speed network applications. Although traditional hardware development flows struggle to be responsive, hardware construction languages (HCLs) bring new opportunities to hardware development. This article showcases how Chisel HCL unleashes the power of agile development methodologies through three successive development iterations of a hash-table, a core network processing module in OVHcloud mitigation systems.
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https://hal.archives-ouvertes.fr/hal-03157426
Contributor : Jean Bruant Connect in order to contact the contributor
Submitted on : Wednesday, March 3, 2021 - 10:34:52 AM
Last modification on : Friday, April 1, 2022 - 3:55:58 AM

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Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot. Towards Agile Hardware Designs with Chisel: a Network Use-case. IEEE Design & Test, IEEE, 2021, ⟨10.1109/MDAT.2021.3063339⟩. ⟨hal-03157426⟩

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