Extraction of packaged GaN power transistors parasitics using S-parameters

Loris Pace (1, 2) , N. Defrance (1, 2) , Arnaud Videt (3) , N. Idir , Jean-Claude de Jaeger (1, 2) , Vanessa Avramovic (4)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 PUISSANCE - IEMN - Puissance - IEMN
3 L2EP - Laboratoire d’Électrotechnique et d’Électronique de Puissance - ULR 2697
4 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520

In order to better predict the high-frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances, and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this paper, it is applied to an enhancement-mode GaN high electron mobility transistor (HEMT). The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the nonlinear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer.

Mots clés: Access inductances; access resistances; capacitances; gallium nitride (GaN); power transistors; S-parameters

Domaines: Sciences de l'ingénieur [physics]

Loris Pace, N. Defrance, Arnaud Videt, N. Idir, Jean-Claude de Jaeger, et al.. Extraction of packaged GaN power transistors parasitics using S-parameters. IEEE Transactions on Electron Devices, 2019, 66 (6), pp.2583-2588. ⟨10.1109/TED.2019.2909152⟩. ⟨hal-03140657⟩