WPMVP'20: Proceedings of the 2020 Sixth Workshop on Programming Models for SIMD/Vector Processing

Jan Eitzinger , Lionel Lacassagne (1)

1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce

SIMD processing is still a main driver of performance in general-purpose processor architectures besides multi-core technology. Both technologies increase the potential performance by factors, but have to be explicitly utilized by the software. To expose those different levels of parallelism in a productive and manageable way is still an active area of research. NVIDIA stirred the programming interface scene with the development of a simple yet efficient performance-oriented application programmer interface. OpenACC, OpenMP 4.0, OpenCL, Cilk+ and icpc are just examples for many choices available. Additionally, established optimizing compilers still improve significantly in unleashing the SIMD potential. Notable developments on the hardware side include relaxation of alignment requirements and more powerful scatter/gather and shuffle instructions. Recent developments include the introduction of 512-bit SIMD units in general purpose processors (AVX512) and new innovations as the Scalable Vector Extension (SVE) for the ARMv8-A architecture or the NEC SX Aurora TSUBASA vector processors.

Domaines: Traitement du signal et de l'image [eess.SP]; Vision par ordinateur et reconnaissance de formes [cs.CV]; Traitement du signal et de l'image [eess.SP]; Traitement des images [eess.IV]; Mathématique discrète [cs.DM]; Génie logiciel [cs.SE]; Calcul parallèle, distribué et partagé [cs.DC]; Arithmétique des ordinateurs; Architectures Matérielles [cs.AR]; Algorithme et structure de données [cs.DS]

Jan Eitzinger, Lionel Lacassagne. WPMVP'20: Proceedings of the 2020 Sixth Workshop on Programming Models for SIMD/Vector Processing. ACM, 2020, ⟨10.1145/3380479⟩. ⟨hal-03126845⟩