Skip to Main content Skip to Navigation
Journal articles

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance

Complete list of metadata

https://hal.archives-ouvertes.fr/hal-03065940
Contributor : Laurence Ben Tito <>
Submitted on : Tuesday, December 15, 2020 - 8:47:39 AM
Last modification on : Tuesday, February 23, 2021 - 5:12:17 PM

Licence


Distributed under a Creative Commons Attribution - NonCommercial 4.0 International License

Identifiers

Collections

TIMA | UGA | CNRS

Citation

Muhammed Ceylan Morgül, L. Frontini, O. Tunali, Lorena Anghel, V. Ciriani, et al.. Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance. IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2020, ⟨10.1109/TNANO.2020.3044017⟩. ⟨hal-03065940⟩

Share

Metrics

Record views

26