A seamless DFT/FFT self-adaptive architecture for embedded radar applications

Julien Mazuet (1, 2) , Michel Narozny (2) , Catherine Dezan (1) , Jean-Philippe Diguet (3)

1 Lab-STICC_UBO_CACS_MOCS
2 THALES Airborne Systems [Elancourt]
3 Lab-STICC_UBS_CACS_MOCS

Radar is one of the domains where adaptability is paramount and algorithms must be adapted to system state. However, most systems include static implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. The classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. In embedded systems, FPGA dynamic partial reconfiguration (DPR) is a promising solution to reuse scarce resources. In this paper, we use DPR for radar processing in order to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a new architecture and decision method that relies on Radar QoS for enabling an efficient self-adaptive solution. Finally, we provide a case study and a hardware-in-loop simulation with a reconfigurable radar implementation.

Mots clés: FPGA; DPR; radar; QoS; DFT

Domaines: Architectures Matérielles [cs.AR]

Julien Mazuet, Michel Narozny, Catherine Dezan, Jean-Philippe Diguet. A seamless DFT/FFT self-adaptive architecture for embedded radar applications. The International Conference on Field-Programmable Logic and Applications (FPL), Aug 2020, Gothenburg (virtual ), Sweden. ⟨10.1109/FPL50879.2020.00029⟩. ⟨hal-03047989⟩