P-type SiC layers formed by VLS induced selective epitaxial growth

Mihai Lazar (1, 2) , C Jacquier (3) , Ch Dubois (4) , Christophe Raynaud (1, 2) , G Ferro (3) , Dominique Planson (1, 2) , Pierre Brosselard (1, 5, 2) , Y Monteil (3)

1 CEGELY - Centre de génie électrique de Lyon
2 INSA Lyon - Institut National des Sciences Appliquées de Lyon
3 LMI - Laboratoire des Multimatériaux et Interfaces
4 LPM - Laboratoire de physique de la matière
5 ISL - Institut franco-allemand de recherches de Saint-Louis

Unipolar SiC devices like Schottky diodes, MESFET and JFET are already or will be soon commercialized. Different universities or industrial research teams have published a non-negligible number of bipolar device demonstrators in SiC. Nevertheless large efforts were mainly targeted in increasing the breakdown voltage. Results on 19.5kV bipolar diodes were published [1]. In spite of that, the development of SiC bipolar devices is slowed down due to the low currents which are obtained in forward polarization. This is due firstly to the material quality which limits the device area and secondly to the high resistances of the SiC p-type layers and the ohmic contacts on these layers. Diminishing the SiC p-type layers resistance is difficult by classical process due to the solubility limit of dopants during the CVD epitaxy [2] or the material degradation by ion implantation at high doses. Partial material recovery and dopant activation are obtained after high temperature post-implantation annealing (1700 – 1800°C). In this paper we present SiC p-type material selectively grown at relatively low temperature process by Vapour-Liquid-Solid (VLS).

Domaines: Energie électrique

Mihai Lazar, C Jacquier, Ch Dubois, Christophe Raynaud, G Ferro, et al.. P-type SiC layers formed by VLS induced selective epitaxial growth. European Conference on Silion Carbide and Related Materials (ECSCRM 2004), Sep 2004, Bologne, Italy. ⟨hal-02953086⟩