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Timing-Aware high level power estimation of industrial interconnect module

Résumé : The semiconductor industry is developing smaller transistors and succeeding in increasing their on-chip integration density. Therefore, the computing power of modern Integrated Circuits (IC) is constantly increasing and their application domains are becoming countless. However, the increasing complexity leads to higher power consumption and more challenging designs. In order to address these issues and to differentiate themselves in the market, manufacturers and System-On-Chip (SoC) engineers are devoting tremendous effort to researching new development strategies. Numerous studies have shown that one of the essential steps to be taken is to review the early stages of the design flow and in particular to integrate simulation-based modeling and verification at higher level of abstraction. In this paper we address this gap and present a proof of concept of an academic power estimation and management methodology, called PwClkARCH, on an NXP intellectual property (IP). Memory power estimation has been improved using DRAMPower. The results prove that with PwClkARCH, we are able to perform mixed performance/power/energy modeling on Approximately Timed (AT) SystemC models, which are widely used for architecture exploration and optimization. Our methodology allows to dynamically extract power metrics and allows to apply power management and reduction strategies, while considering the functional model activity, the power management and reduction strategies and the memory systems consumption.
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Contributor : Sophie Gaffé-Clément <>
Submitted on : Monday, September 28, 2020 - 10:12:28 PM
Last modification on : Monday, October 12, 2020 - 10:30:51 AM


  • HAL Id : hal-02951763, version 1



Amal Ben Ameur, Antonio Genov, François Verdier, Loic Leconte. Timing-Aware high level power estimation of industrial interconnect module. Design and Verification Conference and Exhibition" (DVCON), Oct 2020, conférence virtuelle, France. ⟨hal-02951763⟩



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