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Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV

Erwan Moréac 1 El Mehdi Abdali 2 François Berry 2 Dominique Heller 1 Jean-Philippe Diguet 1, 3 
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Hardware in the loop simulation has become a fundamental tool for the safe and rapid development of embedded systems. Dynamically and partially reconfigurable FPGA provide an energy efficient solution for high performance computing in embedded systems, such as computer vision, with limited resources. Finally 3D simulation with realistic physics simulation is required by designers of Unmanned Aerial Vehicle (UAV) and related missions. The combination of the three techniques are required to design UAV with reconfigurable HW/SW embedded systems that can self-adapt to different mission phases according to environment changes. But they require different complex and specific skills from separated communities and so are not considered simultaneously. In this paper we demonstrate a complete framework that we apply to a UAV case simulated with the well adopted Gazebo 3D simulation tool including the Ardupilot model. According to usual practices in Robotics, we use Robot Operating System (ROS) middleware over Linux that we implement on a separated Intel Cyclone V FPGA board including HW/SW interfaces. As a convincing case study we implement, besides software classical navigation tasks, a vision-based emergency-landing security task and a detect and tracking classic mission application (TLD) that can run in different HW and SW versions dynamically configured on the FPGA according to mission steps simulated with Gazebo.
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Submitted on : Thursday, September 24, 2020 - 4:43:54 PM
Last modification on : Thursday, May 12, 2022 - 8:28:02 AM
Long-term archiving on: : Thursday, December 3, 2020 - 5:17:01 PM


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  • HAL Id : hal-02948474, version 1


Erwan Moréac, El Mehdi Abdali, François Berry, Dominique Heller, Jean-Philippe Diguet. Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV. 31st International Workshop on Rapid System Prototyping (RSP), Sep 2020, Virtual Conference (ESWEEK), France. ⟨hal-02948474⟩



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