Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN

Plinio Bau (1, 2) , Marc Cousineau (3) , Bernardo Cougo (1) , Frédéric Richardeau (3) , Nicolas C. Rouger (3)

1 IRT Saint Exupéry - Institut de Recherche Technologique
2 LAPLACE - LAboratoire PLasma et Conversion d'Energie
3 LAPLACE-CS - Convertisseurs Statiques

The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1.59 GHz using an 1pF integrated capacitor to address a switching speed of 175 V/ns is demonstrated. Experimental results and simulations using accurate technology models confirms the theory. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power IC.

Domaines: Micro et nanotechnologies/Microélectronique; Energie électrique

Plinio Bau, Marc Cousineau, Bernardo Cougo, Frédéric Richardeau, Nicolas C. Rouger. Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN. 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sep 2020, Vienna ( virtual ), Austria. pp.106-109, ⟨10.1109/ISPSD46842.2020.9170106⟩. ⟨hal-02920181⟩