R. Khatoun and S. Zeadally, Smart cities: Concepts, architectures, research opportunities, Commun. ACM, vol.59, issue.8, pp.46-57, 2016.

F. N. Najm, A survey of power estimation techniques in vlsi circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.2, issue.4, pp.446-455, 1994.

P. Landman, High-level power estimation, Proceedings of the 1996 International Symposium on Low Power Electronics and Design, ser. ISLPED '96, pp.29-35, 1996.

E. Macii, M. Pedram, and F. Somenzi, High-level power modeling, estimation, and optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, issue.11, pp.1061-1079, 1998.

S. Reda and A. N. Nowroz, Power modeling and characterization of computing devices, Foundations and Trends R in Electronic Design Automation, vol.6, issue.2, pp.121-216, 2012.

A. B. Darwish, M. A. El-moursy, and M. A. Dessouky, Power Modeling and Characterization, pp.47-57, 2020.

J. Deschamps, Hardware implementation of finite-field arithmetic, 2009.

. Xilinx, About Post-Synthesis and Post-Implementation Timing Simulation, 2012.

I. Kuon and J. Rose, Measuring the gap between fpgas and asics, IEEE Transactions on computer-aided design of integrated circuits and systems, vol.26, issue.2, pp.203-215, 2007.

Y. Nasser, C. Sau, J. Prévotet, T. Fanni, F. Palumbo et al., Neupow: Artificial neural networks for power and behavioral modeling of arithmetic components in 45nm asics technology, Proceedings of the 16th ACM International Conference on Computing Frontiers, ser. CF '19, pp.183-189, 2019.
URL : https://hal.archives-ouvertes.fr/hal-02165618

D. Bellizia, D. Cellucci, V. D. Stefano, G. Scotti, and A. Trifiletti, Novel measurements setup for attacks exploiting static power using dc pico-ammeter, 2017 European Conference on Circuit Theory and Design (ECCTD), pp.1-4, 2017.

P. Gaillardon, E. Beigne, S. Lesecq, and G. D. Micheli, A survey on low-power techniques with emerging technologies: From devices to systems, J. Emerg. Technol. Comput. Syst, vol.12, issue.2, pp.1-12, 2015.

P. Gupta and A. B. Kahng, Quantifying error in dynamic power estimation of cmos circuits, Fourth International Symposium on Quality Electronic Design, pp.273-278, 2003.

S. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis &Amp; Design, 2003.

L. Shang, A. S. Kaviani, and K. Bathala, Dynamic power consumption in virtex TM -ii fpga family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, pp.157-164, 2002.

. Xilinx, TI Power Solutions for measuring power on Xilinx Evaluation Kits, 2018.

A. Nafkha and Y. Louet, Accurate measurement of power consumption overhead during fpga dynamic partial reconfiguration, 2016 International Symposium on Wireless Communication Systems (ISWCS), pp.586-591, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01413268

M. A. Rihani, F. Nouvel, J. Prévotet, M. Mroue, J. Lorandel et al., Dynamic and partial reconfiguration power consumption runtime measurements analysis for zynq soc devices, 2016 International Symposium on Wireless Communication Systems (ISWCS), pp.592-596, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01413269

R. Jevtic and C. Carreras, Power measurement methodology for fpga devices, IEEE Transactions on Instrumentation and Measurement, vol.60, issue.1, pp.237-247, 2011.

J. Oliver, F. Veirano, D. Bouvier, and E. Boemo, A low cost system for self measurements of power consumption in field programmable gate arrays, Journal of Low Power Electronics, vol.13, issue.1, 2017.

M. Najem, P. Benoit, F. Bruguier, G. Sassatelli, and L. Torres, Method for dynamic power monitoring on FPGAs, Conference Digest -24th International Conference on Field Programmable Logic and Applications, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01139163

J. J. Davis, E. Hung, J. M. Levine, E. A. Stott, P. Y. Cheung et al., KAPow: High-accuracy, low-overhead online per-module power estimation for FPGA designs, ACM Transactions on Reconfigurable Technology and Systems, 2018.

Z. Lin, S. Sinha, and W. Zhang, An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.

J. P. Oliver, F. Favaro, and E. Boemo, A framework to compare estimated and measured power consumption on fpgas, Journal of Low Power Electronics, vol.15, issue.4, pp.329-337, 2019.

C. Tsui, M. Pedram, and A. M. Despain, Exact and approximate methods for calculating signal and transition probabilities in fsms, 31st Design Automation Conference, pp.18-23, 1994.

D. Marculescu, R. Marculescu, and M. Pedram, Stochastic sequential machine synthesis targeting constrained sequence generation, 33rd Design Automation Conference Proceedings, pp.696-701, 1996.

J. Monteiro, S. Devadas, and B. Lin, A methodology for efficient estimation of switching activity in sequential logic circuits, 31st Design Automation Conference, pp.12-17, 1994.

F. N. Najm, Transition density: A new measure of activity in digital circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.12, issue.2, pp.310-323, 1993.

C. Tsui, M. Pedram, and A. M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

, IEEE, pp.224-228, 1993.

R. Marculescu, D. Marculescu, and M. Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, pp.294-299, 1994.

P. H. Schneider and S. Krishnamoorthy, Effects of correlations on accuracy of power analysis-an experimental study, Proceedings of 1996 International Symposium on Low Power Electronics and Design, pp.113-116, 1996.

S. Garg, S. Tata, and R. Arunachalam, Static transition probability analysis under uncertainty, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.380-386, 2004.

L. Lavagno, I. L. Markov, G. Martin, and L. K. Scheffer, Electronic design automation for IC implementation, circuit design, and process technology, 2017.

L. W. Nagel, Spice2: A computer program to simulate semiconductor circuits, 1975.

C. X. Huang, B. Zhang, A. Deng, and B. Swirski, The design and implementation of powermill, Proceedings ofthe International Symposium on Low Power Design. Citeseer, 1995.

C. Piguet, C. Low-power, and . Circuits, , 2018.

M. Bushnell and V. , Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits, vol.17, 2004.

S. Alipour, B. Hidaji, and A. S. Pour, Circuit level, static power, and logic level power analyses, 2010 IEEE International Conference on Electro/Information Technology, EIT2010, 2010.

R. Burch, F. Najm, P. Yang, and T. Trick, Mcpower: A monte carlo approach to power estimation, ICCAD, vol.92, pp.90-97, 1992.

M. G. Xakellis and F. N. Najm, Statistical estimation of the switching activity in digital circuitsy, 31st Design Automation Conference, pp.728-733, 1994.

Y. Park and E. Park, Statistical power estimation of cmos logic circuits with variable errors, Electronics Letters, vol.34, issue.11, pp.1054-1056, 1998.

Y. A. Durrani and T. Riesgo, Efficient power analysis approach and its application to system-on-chip design, Microprocessors and Microsystems, 2016.

G. Verma, C. Dabas, A. Goel, M. Kumar, and V. Khare, Clustering based power optimization of digital circuits for FPGAs, Journal of Information and Optimization Sciences, 2017.

. Synopsys, Delivers accurate dynamic and leakage power analysis, 2018.

R. Cadence, Genus synthesis solution, pp.2018-2026, 2018.

. Xilinx, Xilinx power estimator user guide: Ug440, 2017.

-. , XPower Analyzer Overview, 2014.

A. K. Sultania, C. Zhang, D. K. Gandhi, and F. Zhang, Power Analysis and Optimization, pp.177-187, 2017.

P. E. Estimators, Power analyzer

J. Lamoureux and S. J. Wilton, Activity estimation for fieldprogrammable gate arrays, 2006 International Conference on Field Programmable Logic and Applications, pp.1-8, 2006.

J. B. Goeders and S. J. Wilton, Versapower: Power estimation for diverse fpga architectures, 2012 International Conference on Field-Programmable Technology, pp.229-234, 2012.

X. Tang, E. Giacomin, G. D. Micheli, and P. E. Gaillardon, FPGA-SPICE: A simulation-based architecture evaluation framework for FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019.

F. N. Najm, A survey of power estimation techniques in vlsi circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.2, issue.4, pp.446-455, 1994.

T. Arslan, A. Erdogan, and D. Horrocks, Low power design for dsp: methodologies and techniques, Microelectronics Journal, vol.27, issue.8, pp.731-744, 1996.

R. Burch, F. N. Najm, P. Yang, and T. N. Trick, A monte carlo approach for power estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, issue.1, pp.63-71, 1993.

B. S. Landman and R. L. Russo, On a pin versus block relationship for partitions of logic graphs, IEEE Transactions on Computers, vol.20, issue.12, pp.1469-1479, 1971.

F. N. Najm, Transition density: a new measure of activity in digital circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.12, issue.2, pp.310-323, 1993.

H. A. Hassan, M. Anis, and M. Elmasry, Total power modeling in fpgas under spatial correlation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, issue.4, pp.578-582, 2009.

J. A. Clarke, A. A. Gaffar, and G. A. Constantinides, Parameterized logic power consumption models for fpga-based arithmetic, International Conference on Field Programmable Logic and Applications, pp.626-629, 2005.

Z. Chen and K. Roy, A power macromodeling technique based on power sensitivity, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), pp.678-683, 1998.

Z. Chen, K. Roy, and E. K. Chong, Estimation of power sensitivity in sequential circuits with power macromodeling application, 1998 IEEE/ACM International Conference on Computer-Aided Design, pp.468-472, 1998.

X. Tang, L. Wang, and H. Xu, An accurate dynamic power model on fpga routing resources, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp.1-3, 2012.

R. Jevtic, B. Jovanovic, and C. Carreras, Power estimation of dividers implemented in fpgas, Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI, ser. GLSVLSI '11, pp.313-318, 2011.

J. Das, A. Lam, S. J. Wilton, P. H. Leong, and W. Luk, An analytical model relating fpga architecture to logic density and depth, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.12, pp.2229-2242, 2011.

K. K. Poon, S. J. Wilton, and A. Yan, A detailed power model for field-programmable gate arrays, ACM Trans. Des. Autom. Electron. Syst, vol.10, issue.2, pp.279-302, 2005.

Y. Leow, A. Akoglu, and S. Lysecky, An analytical model for evaluating static power of homogeneous fpga architectures, ACM Transactions on Reconfigurable Technology and Systems, vol.6, issue.4, p.2013

H. Mehri and B. Alizadeh, Analytical performance model for fpgabased reconfigurable computing, Microprocessors and Microsystems, vol.39, issue.8, pp.796-806, 2015.

A. Soni, Y. K. Leow, and A. Akoglu, Post-routing analytical wirelength model for homogeneous fpga architectures, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp.1-8, 2018.

A. Raghunathan, S. Dey, and N. K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of International Conference on Computer Aided Design, pp.158-165, 1996.

S. Gupta and F. N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual Design Automation Conference, pp.365-370, 1997.

M. Barocci, L. Benini, A. Bogliolo, B. Riccó, and G. De-micheli, Lookup table power macro-models for behavioral library components, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp.173-181, 1999.

S. Gupta and F. N. Najm, Power modeling for high-level power estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.8, issue.1, pp.18-29, 2000.

Y. A. Durrani, T. Riesgo, and F. Machado, Statistical power estimation for register transfer level, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, pp.522-527, 2006.

Y. A. Durrani and T. Riesgo, Power estimation for intellectual property-based digital systems at the architectural level, J. King Saud Univ. Comput. Inf. Sci, vol.26, issue.3, pp.287-295, 2014.

S. Gupta and F. N. Najm, Power macro-models for dsp blocks with application to high-level synthesis, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), pp.103-105, 1999.

G. Bernacchia and M. C. Papaefthymiou, Analytical macromodeling for high-level power estimation, IEEE/ACM International Conference on Computer-Aided Design, pp.280-283, 1999.

L. Shang and N. K. Jha, High-level power modeling of cplds and fpgas, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD, pp.46-51, 2001.

A. Bogliolo, L. Benini, G. De-micheli, G. D. Micheli, and G. De-micheli, Regression-based rtl power modeling, ACM Trans. Des. Autom. Electron. Syst, vol.5, issue.3, pp.337-372, 2000.

A. Lakshminarayana, S. Ahuja, and S. Shukla, High level power estimation models for fpgas, 2011 IEEE Computer Society Annual Symposium on VLSI, pp.7-12, 2011.

R. Jevtic and C. Carreras, Power estimation of embedded multiplier blocks in fpgas, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, issue.5, pp.835-839, 2010.

T. Jiang, X. Tang, and P. Banerjee, Macro-models for high level area and power estimation on fpgas, Proceedings of the 14th ACM Great Lakes Symposium on VLSI, ser. GLSVLSI '04, pp.162-165, 2004.

L. Deng, K. Sobti, Y. Zhang, and C. Chakrabarti, Accurate area, time and power models for fpga-based implementations, Journal of Signal Processing Systems, vol.63, issue.1, pp.39-50, 2011.

B. M. Chalbi-najoua and B. Mohamed, Accurate dynamic power model for fpga based implementations, IJCSI International Journal of Computer Science Issues, vol.9, issue.2, 2012.

G. Verma, V. Khare, and M. Kumar, More precise fpga power estimation and validation tool (fpev tool) for low power applications, Wireless Personal Communications, vol.106, issue.4, pp.2237-2246, 2019.

J. J. Davis, J. M. Levine, E. A. Stott, E. Hung, P. Y. Cheung et al., Stripe: Signal selection for runtime power estimation, 2017 27th International Conference on Field Programmable Logic and Applications, pp.1-8, 2017.

D. Kim, J. Zhao, J. Bachrach, and K. Asanovi?, Simmani: Runtime power modeling for arbitrary rtl with automatic signal selection, pp.1050-1062, 2019.

M. Makni, S. Niar, M. Baklouti, and M. Abid, Hape: A highlevel area-power estimation framework for fpga-based accelerators, Microprocessors and Microsystems, vol.63, pp.11-27, 2018.

N. Abdelli, A. Fouilliart, N. Julien, and E. Senn, High-level power estimation of fpga, 2007 IEEE International Symposium on Industrial Electronics, pp.925-930, 2007.

D. Helms, R. Eilers, M. Metzdorf, and W. Nebel, Leakage models for high level power estimation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1-1, 2017.

S. Mars, A. E. Mourabit, A. Moussa, Z. Asrih, and I. E. Hajjouji, High-level performance estimation of image processing design using fpga, 2016 International Conference on Electrical and Information Technologies (ICEIT), pp.543-546, 2016.

F. Scarselli and A. C. Tsoi, Universal approximation using feedforward neural networks: A survey of some existing methods, and some new results, Neural Netw, vol.11, issue.1, pp.15-37, 1998.

W. Hsieh, C. Shiue, and C. Liu, A novel approach for highlevel power modeling of sequential circuits using recurrent neural networks, 2005 IEEE International Symposium on Circuits and Systems, pp.3591-3594, 2005.

X. Gao, Y. Yan, Y. Cao, and W. Qiang, Neural network macromodel for high-level power estimation of cmos circuits, 2005 International Conference on Neural Networks and Brain, vol.2, pp.1009-1014, 2005.

K. Roy, Neural network based macromodels for high level power estimation, International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007), vol.2, pp.159-163, 2007.

L. Hou, X. Wu, and W. Wu, Neural network based power estimation on chip specification, The 3rd International Conference on Information Sciences and Interaction Sciences, pp.187-190, 2010.

A. A. Sagahyroon and J. A. Abdalla, Dynamic and leakage power estimation in register files using neural networks, Circuits and Systems, vol.3, issue.02, p.119, 2012.

P. Ramanathan, B. Surendiran, and P. Vanathi, Power estimation of benchmark circuits using artificial neural networks, Pensee, vol.75, issue.9, 2013.

J. Lorandel, J. Prévotet, and M. Hélard, Efficient modelling of fpga-based ip blocks using neural networks, 2016 International Symposium on Wireless Communication Systems (ISWCS), pp.571-575, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01376302

A. N. Tripathi and A. Rajawat, Fast and efficient power estimation model for fpga based designs, Microprocessors and Microsystems, vol.59, pp.37-45, 2018.

Y. Zhou, H. Ren, Y. Zhang, B. Keller, B. Khailany et al., Primal: Power inference using machine learning, Proceedings of the 56th Annual Design Automation Conference, pp.1-6, 2019.

H. Dhotre, S. Eggersglüß, K. Chakrabarty, and R. Drechsler, Machine learning-based prediction of test power, 2019 IEEE European Test Symposium (ETS), pp.1-6, 2019.

Y. Nasser, C. Sau, J. Prévotet, T. Fanni, F. Palumbo et al., NeuPow: A CAD Methodology for High Level Power Estimation Based on Machine Learning, ACM Transactions on Design Automation of Electronic Systems, 2020.
URL : https://hal.archives-ouvertes.fr/hal-02518770

A. Suissa, O. Romain, J. Denoulet, K. Hachicha, and P. Garda, Empirical method based on neural networks for analog power modeling, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.5, pp.839-844, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01198824

F. Scarselli and A. C. Tsoi, Universal approximation using feedforward neural networks: A survey of some existing methods, and some new results, Neural networks, vol.11, issue.1, pp.15-37, 1998.

Y. Nasser, J. Prévotet, and M. Hélard, Power modeling on fpga: A neural model for rt-level power estimation, Proceedings of the 15th ACM International Conference on Computing Frontiers, ser. CF '18, pp.309-313, 2018.
URL : https://hal.archives-ouvertes.fr/hal-01760342