RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey

Yehya Nasser (1) , Jordane Lorandel (1) , Jean-Christophe Prevotet (1) , Maryline Hélard (2)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 IETR - Institut d'Electronique et de Télécommunications de Rennes

Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works.

Mots clés: Index Terms-Power consumption; power modelling; power estimation; high-level power estimation; FPGA; ASIC; tools

Domaines: Sciences de l'ingénieur [physics]; Electronique

Yehya Nasser, Jordane Lorandel, Jean-Christophe Prevotet, Maryline Hélard. RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40 (3), pp.479-493. ⟨10.1109/TCAD.2020.3003276⟩. ⟨hal-02866921⟩