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RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey

Abstract : Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works.
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Contributor : Nasser Nasser <>
Submitted on : Friday, June 12, 2020 - 8:08:27 PM
Last modification on : Saturday, July 11, 2020 - 3:16:23 AM


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Yehya Nasser, Jordane Lorandel, Jean-Christophe Prevotet, Maryline Hélard. RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020. ⟨hal-02866921⟩



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