Energy Efficient Acceleration of Floating Point Applications onto CGRA

Satyajit Das (1, 2) , Rohit Prasad (1) , Kevin Martin (1) , Philippe Coussy (1)

1 Lab-STICC_UBS_CACS_MOCS
2 ITT Palakkad - Indian Institut of Technology [Palakkad]

In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications. Experimental results show that the proposed accelerator achieves a maximum of 4.61× speed-up compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative of wide range of EEG signal processing applications with an area overhead of 1.9×. The proposed CGRA achieves a maximum of 6.5× energy efficiency compared to the CPU.

Domaines: Architectures Matérielles [cs.AR]

Satyajit Das, Rohit Prasad, Kevin Martin, Philippe Coussy. Energy Efficient Acceleration of Floating Point Applications onto CGRA. ICASSP, May 2020, Barcelona, Spain. ⟨hal-02614908⟩