Scalable compact modeling of trap generation near the EB spacer oxide interface in SiGe HBTs - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Solid-State Electronics Année : 2020

Scalable compact modeling of trap generation near the EB spacer oxide interface in SiGe HBTs

Résumé

This paper presents a physics-based scalable formulation for interface trap generation in the vicinity of the emitter-base spacer oxide interface in advanced SiGe HBTs. Aging tests were performed for various emitter dimensions to investigate the scalability of the dynamics of hot-carrier degradation. An improved formulation of the bond dissociation rate is also proposed incorporating a scaling rule depending on the avalanche current density. The hydrogen diffusion through the EB spacer has been modeled using an RC ladder network and has been scaled according to the hydrogen diffusion volume. Its accuracy has been validated over a wide range of aging tests and various geometry features.
Fichier principal
Vignette du fichier
SSE_Article_Revised_Version_Clean.pdf (727.46 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-02541991 , version 1 (14-04-2020)

Identifiants

Citer

Marine Couret, Mathieu Jaoul, François Marc, Chhandak Mukherjee, Didier Celi, et al.. Scalable compact modeling of trap generation near the EB spacer oxide interface in SiGe HBTs. Solid-State Electronics, 2020, pp.107819. ⟨10.1016/j.sse.2020.107819⟩. ⟨hal-02541991⟩
57 Consultations
61 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More