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Conference papers
Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter
Abstract : This paper presents a functional design and modeling of a successive approximation analog to digital converter(SAR ADC). The SAR ADC is described in VHDL-AMS behavior models and transistor level circuit netlists using the 0.13μm technology and supply voltage equals to 1.2V. The system was simulated using a signal commercial simulator.
https://hal.archives-ouvertes.fr/hal-02535544
Contributor : Lip6 Publications <>
Submitted on : Tuesday, April 7, 2020 - 4:20:51 PM
Last modification on : Thursday, April 9, 2020 - 1:22:35 AM
Contributor : Lip6 Publications <>
Submitted on : Tuesday, April 7, 2020 - 4:20:51 PM
Last modification on : Thursday, April 9, 2020 - 1:22:35 AM
