TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Rohit Prasad (1, 2) , Satyajit Das (3) , Kevin Martin (1) , Giuseppe Tagliavini (2) , Philippe Coussy (1) , Luca Benini (2, 4) , Davide Rossi (2)

1 Lab-STICC_UBS_CACS_MOCS
2 UNIBO - Alma Mater Studiorum Università di Bologna = University of Bologna
3 ITT Palakkad - Indian Institut of Technology [Palakkad]
4 ETH Zürich - Eidgenössische Technische Hochschule - Swiss Federal Institute of Technology [Zürich]

In recent years, Coarse Grain Reconfigurable Architecture (CGRA) accelerators have been increasingly deployed in Internet-of-Things (IoT) end nodes. A modern CGRA has to support and efficiently accelerate both integer and floating-point (FP) operations. In this paper, we propose an ultra-low-power tunable-precision CGRA architectural template, called TRANSprecision floating-point Programmable archItectuRE (TRANSPIRE), and its associated compilation flow supporting both integer and FP operations. TRANSPIRE employs transprecision computing and multiple Single Instruction Multiple Data (SIMD) to accelerate FP operations while boosting energy efficiency as well. Experimental results show that TRANSPIRE achieves a maximum of 10.06× performance gain and consumes 12.91× less energy w.r.t. a RISC-V based CPU with an enhanced ISA supporting SIMD-style vectorization and FP data-types, while executing applications for near-sensor computing and embedded machine learning, with an area overhead of 1.25× only.

Domaines: Architectures Matérielles [cs.AR]

Rohit Prasad, Satyajit Das, Kevin Martin, Giuseppe Tagliavini, Philippe Coussy, et al.. TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. Design, Automation and Test in Europe Conference (DATE), Mar 2020, Grenoble, France. ⟨hal-02510931⟩