Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS

David Gaidioz (1, 2) , Magali Dematos (1) , Andreia Cathelin (2) , Yann Deval (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 STMicroelectronics

This paper presents a Pseudo-differential Ring- VCO (PRVCO) architecture optimized to improve by more than a factor of two the phase noise performance of regular single-ended inverter-based Ring-VCO (RVCO). Two RVCO topologies are compared and integrated in 28nm FD-SOI CMOS technology from STMicroelectronics. Based on a double tuning approach, each oscillator presents a Frequency Tuning Range (FTR) between 0.7 GHz and 2.8 GHz (120 % of FTR). The coarse tuning is realized by the local supply voltage variation, while the fine tuning is obtained via the transistors wide range body biasing specific to FD-SOI. Under typical configuration, the PRVCO presents a phase noise (PN) performance of – 95.7 dBc/Hz at 1 MHz offset frequency, which represents a 4 dB improvement compared to the inverter-based RVCO phase noise at 1.7 GHz. Both fabricated RVCOs performances are compared to the state-of-art regarding their oscillator’s and VCO’s Figure of Merit (FoM).

Domaines: Electronique; Micro et nanotechnologies/Microélectronique

David Gaidioz, Magali Dematos, Andreia Cathelin, Yann Deval. Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS. IEEE International Symposium On Circuits and Systems, May 2020, Seville, Spain. ⟨hal-02499134⟩