Tightness and Computation Assessment of Worst-Case Delay Bounds in Wormhole Networks-On-Chip

Frédéric Giroudot (1) , Ahlem Mifdaoui (1)

1 DISC - Département d'Ingénierie des Systèmes Complexes

This paper addresses the problem of worst-case timing analysis in wormhole Networks-On-Chip (NoCs). We consider our previous work [5] for computing maximum delay bounds using Network Calculus, called the Buffer-Aware Worst-case Timing Analysis (BATA). The latter allows the computation of delay bounds for a large panel of wormhole NoCs, e.g., handling priority-sharing, Virtual Channel Sharing and buffer backpressure.In this paper, we provide further insights into the tightness and computation issues of the worst-case delay bounds yielded by BATA. Our assessment shows that the gap between the computed delay bounds and the worst-case simulation results is reasonably small (70% tightness on average). Furthermore, BATA provides good delay bounds for medium-scale configurations within less than one hour. Finally, we evaluate the yielded improvements with BATA for a realistic use-case against a recent state-of-the-art approach. This evaluation shows the applicability of BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

Mots clés: Networks-on-chip; Network Calculus; Wormhole routing; VC-sharing; Backpressure; Buffer

Domaines: Réseaux et télécommunications [cs.NI]

Frédéric Giroudot, Ahlem Mifdaoui. Tightness and Computation Assessment of Worst-Case Delay Bounds in Wormhole Networks-On-Chip. 27th International Conference on Real-Time Networks and Systems (RTNS 2019), Nov 2019, Toulouse, France. pp.19-29. ⟨hal-02482683⟩