Performance and complexity of block turbo decoder circuits

Patrick Adde (1) , Ramesh Pyndiah (1) , Olivier Raoul (2)

1 ELEC - Département Electronique
2 SC - Département Signal et Communications

This paper presents the latest results on block turbo codes and also an analysis of the possible implementations of a block turbo decoder circuit. Simulation results show that the SNR (signal to noise ratio) required to achieve a BER (Bit Error Rate) of 1O-j with block turbo codes is 2.5zt0.2 dB fiom their Shannon limit for any code rate. We have identified three different solutions for implementing the block turbo decoder circuit. Afer discussing the advantages and disadvantages of the different solutions, we give the results of the degradation of the performance of the block turbo decoder circuit due to data quantization. Finally, in our conclusion, we discuss how to reduce the complexity of the algorithm for its implementation.

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Patrick Adde, Ramesh Pyndiah, Olivier Raoul. Performance and complexity of block turbo decoder circuits. ICECS'96 :Third International Conference on Electronics, Circuits and System, Oct 1996, Rodos, Greece. pp.172 - 175, ⟨10.1109/ICECS.1996.582746⟩. ⟨hal-02480769⟩