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Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits -Part II

Abstract : This paper gives a detailed insight on a machine learning procedure to infer quasistatic quantities of ElectroStatic Discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of Transmission Line Pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article Viale2020.
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Submitted on : Friday, December 27, 2019 - 10:35:04 AM
Last modification on : Monday, September 13, 2021 - 2:44:04 PM

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Benjamin Viale, Bruno Allard. Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits -Part II. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019, pp.1-1. ⟨10.1109/TCAD.2019.2962119⟩. ⟨hal-02424330⟩

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