Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits -Part II

Benjamin Viale (1) , Bruno Allard (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 EE - Ampère, Département Energie Electrique

This paper gives a detailed insight on a machine learning procedure to infer quasistatic quantities of ElectroStatic Discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of Transmission Line Pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article Viale2020.

Mots clés: 28nm FD-SOI; Electrostatic Discharges; ESD; Full-chip ESD verification; Graph-based analysis; Machine learning; Topology-aware ESD network recognition.

Domaines: Energie électrique

Benjamin Viale, Bruno Allard. Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits -Part II. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, pp.1-1. ⟨10.1109/TCAD.2019.2962119⟩. ⟨hal-02424330⟩