Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse

Axel Laborieux (1) , Marc Bocquet (2) , Tifenn Hirtzlin (1) , Jacques-Olivier Klein (1) , L Herrera Diez (1) , Etienne Nowak (3) , Elisa Vianello (3) , Jean-Michel Portal (2) , Damien S Querlioz (1)

1 C2N - Centre de Nanosciences et de Nanotechnologies
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Domaines: Micro et nanotechnologies/Microélectronique

Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, L Herrera Diez, et al.. Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, Genova (virtual), Italy. ⟨10.1109/AICAS48895.2020.9073877⟩. ⟨hal-02403984⟩