C. Maiza, H. Rihani, J. M. Rivas, J. Goossens, S. Altmeyer et al., A survey of timing verification techniques for multi-core realtime systems, 2018.

H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms, Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th, pp.55-64, 2013.

A. Blin, C. Courtaud, J. Sopena, J. Lawall, and G. Muller, Maximizing parallelism without exploding deadlines in a mixed criticality embedded system, Real-Time Systems (ECRTS), pp.109-119, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01268078

N. Nethercote and J. Seward, Valgrind: a framework for heavyweight dynamic binary instrumentation, ACM Sigplan notices, vol.42, pp.89-100, 2007.

L. Breiman, Random forests, Machine learning, vol.45, issue.1, pp.5-32, 2001.

, Sabre board for smart devices based on the i.mx 6quad applications processors

C. Bienia, S. Kumar, J. P. Singh, and K. Li, The parsec benchmark suite: Characterization and architectural implications, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pp.72-81, 2008.

J. D. Mccalpin, Memory bandwidth and machine balance in current high performance computers, IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pp.19-25, 1995.

, MX 6Dual/6Quad Applications Processor Reference Manual, pp.204-205

, PL310 Cache Controller Technical Reference Manual, pp.327-328

P. K. Valsan, H. Yun, and F. Farshchi, Taming non-blocking caches to improve isolation in multicore real-time systems, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

, IEEE, pp.1-12, 2016.

, MX 6Dual/6Quad Applications Processor Reference Manual, p.3852

, The yocto project

, Technical details of preempt rt patch

J. M. Calandrino, H. Leontyev, A. Block, U. C. Devi, and J. H. Anderson, Litmus?rt: A testbed for empirically comparing real-time multiprocessor schedulers, 27th IEEE International Real-Time Systems Symposium (RTSS'06), pp.111-126, 2006.

, Scheduling -rt throttling

, MX 6Dual/6Quad Applications Processor Reference Manual, pp.3834-3835

, Specification, ddr3 sdram, JEDEC, 2010.

C. E. Shannon, A mathematical theory of communication, Bell system technical journal, vol.27, issue.3, pp.379-423, 1948.

S. Hahn, J. Reineke, and R. Wilhelm, Towards compositionality in execution time analysis: definition and challenges, ACM SIGBED Review, vol.12, issue.1, pp.28-36, 2015.

F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion et al., Scikit-learn: Machine learning in Python, Journal of Machine Learning Research, vol.12, pp.2825-2830, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00650905

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge et al., Mibench: A free, commercially representative embedded benchmark suite, Proceedings of the fourth annual IEEE international workshop on workload characterization. WWC-4, pp.3-14, 2001.

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The worst-case execution-time problem-overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems (TECS), vol.7, issue.3, p.36, 2008.

H. Kim, D. De-niz, B. Andersson, M. Klein, O. Mutlu et al., Bounding memory interference delay in cots-based multi-core systems, Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.145-154, 2014.

D. Oehlert, S. Saidi, and H. Falk, Compiler-based extraction of event arrival functions for real-time systems analysis, 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2018.

J. Bin, S. Girbal, D. G. Pérez, A. Grasset, and A. Merigot, Studying corunning avionic real-time applications on multi-core cots architectures, Embedded Real Time Software and Systems conference, vol.15, 2014.
URL : https://hal.archives-ouvertes.fr/hal-02271379

P. Radojkovi?, S. Girbal, A. Grasset, E. Quiñones, S. Yehia et al., On the evaluation of the impact of shared resources in multithreaded cots processors in time-critical environments, ACM Transactions on Architecture and Code Optimization (TACO), vol.8, issue.4, p.34, 2012.

J. Nowotsch and M. Paulitsch, Leveraging multi-core computing architectures in avionics, 2012 Ninth European Dependable Computing Conference, pp.132-143, 2012.

M. Fernández, R. Gioiosa, E. Quiñones, L. Fossati, M. Zulianello et al., Assessing the suitability of the ngmp multi-core processor in the space domain, Proceedings of the tenth ACM international conference on Embedded software, pp.175-184, 2012.

S. Zhuravlev, S. Blagodurov, and A. Fedorova, Addressing shared resource contention in multicore processors via scheduling, ACM Sigplan Notices, vol.45, pp.129-142, 2010.

D. Griffin, B. Lesage, I. Bate, F. Soboczenski, and R. I. Davis, Forecastbased interference: modelling multicore interference from observable factors, Proceedings of the 25th International Conference on Real-Time Networks and Systems, pp.198-207, 2017.

D. Black-schaffer, N. Nikoleris, E. Hagersten, and D. Eklov, Bandwidth bandit: Quantitative characterization of memory contention, Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp.1-10, 2013.

J. Mars, L. Tang, R. Hundt, K. Skadron, and M. L. Soffa, Bubbleup: Increasing utilization in modern warehouse scale computers via sensible co-locations, Proceedings of the 44th annual IEEE/ACM International Symposium on Microarchitecture, pp.248-259, 2011.

J. Funston, M. Lorrillere, A. Fedorova, B. Lepers, D. Vengerov et al., Placement of virtual containers on NUMA systems: A practical and comprehensive model, 2018 USENIX Annual Technical Conference (USENIX ATC 18), pp.281-294, 2018.

D. Iorga, T. Sorensen, and A. F. Donaldson, Do your cores play nicely? a portable framework for multi-core interference tuning and analysis, 2018.

I. Liu, J. Reineke, and E. A. Lee, A pret architecture supporting concurrent programs with composable timing properties, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers, pp.2111-2115, 2010.

M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso et al., T-crest: Time-predictable multi-core architecture for embedded systems, Journal of Systems Architecture, vol.61, issue.9, pp.449-471, 2015.

T. Ungerer, F. Cazorla, P. Sainrat, G. Bernat, Z. Petrov et al., Merasa: Multicore execution of hard real-time applications supporting analyzability, IEEE Micro, vol.30, issue.5, pp.66-75, 2010.

R. E. Kessler and M. D. Hill, Page placement algorithms for large real-indexed caches, ACM Transactions on Computer Systems (TOCS), vol.10, issue.4, pp.338-359, 1992.

R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo et al., Real-time cache management framework for multi-core architectures, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.45-54, 2013.

S. A. Panchamukhi and F. Mueller, Providing task isolation via TLB coloring, 21st IEEE Real-Time and Embedded Technology and Applications Symposium, pp.3-13, 2015.

S. P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, and T. Moscibroda, Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-44, pp.374-385, 2011.

,

H. Yun, R. Mancuso, Z. Wu, and R. Pellizzoni, Palloc: Dram bank-aware memory allocator for performance isolation on multicore platforms, Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.155-166, 2014.

B. C. Ward, J. L. Herman, C. J. Kenna, and J. H. Anderson, Outstanding paper award: Making shared caches more predictable on multicore platforms, 2013 25th Euromicro Conference on Real-Time Systems, pp.157-167, 2013.

N. Kim, B. C. Ward, M. Chisholm, J. H. Anderson, and F. D. Smith, Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning, Real-Time Systems, vol.53, issue.5, pp.709-759, 2017.

S. Fisher, Certifying applications in a multi-core environment: The world's first multi-core certification to sil 4, 2013.

G. Durrieu, M. Faugère, S. Girbal, D. G. Pérez, C. Pagetti et al., Predictable flight management system implementation on a multicore processor, Embedded Real Time Software (ERTS'14), 2014.
URL : https://hal.archives-ouvertes.fr/hal-01121700

A. Schranzhofer, R. Pellizzoni, J. Chen, L. Thiele, and M. Caccamo, Timing analysis for resource access interference on adaptive resource arbiters, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp.213-222, 2011.

R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell et al., A predictable execution model for cots-based embedded systems, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp.269-279, 2011.

X. Jean, Hypervisor control of cots multicores processors in order to enforce determinism for future avionics equipment, 2015.
URL : https://hal.archives-ouvertes.fr/tel-01341758

Q. Perret, P. Maurere, E. Noulard, C. Pagetti, P. Sainrat et al., Temporal isolation of hard real-time applications on many-core processors, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.1-11, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01585055

S. Girbal, X. Jean, J. Le-rhun, D. G. Pérez, and M. Gatti, Deterministic platform software for hard real-time systems using multi-core cots, Digital Avionics Systems Conference (DASC), 2015 IEEE/AIAA 34th, pp.8-12, 2015.

A. Kritikakou, C. Pagetti, O. Baldellon, M. Roy, and C. Rochange, Runtime control to increase task parallelism in mixed-critical systems, 2014 26th Euromicro Conference on Real-Time Systems, pp.119-128, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01015476

A. Kritikakou, C. Rochange, M. Faugère, C. Pagetti, M. Roy et al., Distributed run-time wcet controller for concurrent critical tasks in mixed-critical systems, Proceedings of the 22nd International Conference on Real-Time Networks and Systems, p.139, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01096102