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Improving Prediction Accuracy of Memory Interferences for Multicore Platforms

Abstract : Memory interferences may introduce important slowdowns in applications running on COTS multi-core processors. They are caused by concurrent accesses to shared hardware resources of the memory system. The induced delays are difficult to predict, making memory interferences a major obstacle to the adoption of COTS multi-core processors in real-time systems. In this article, we propose an experimental characterization of ap-plications' memory consumption to determine their sensitivity to memory interferences. Thanks to a new set of microbenchmarks, we show the lack of precision of a purely quantitative characterization. To improve accuracy, we define new metrics quantifying qualitative aspects of memory consumption and implement a profiling tool using the VALGRIND framework. In addition, our profiling tool produces high resolution profiles allowing us to clearly distinguish the various phases in applications' behavior. Using our microbenchmarks and our new characterization, we train a state-of-the-art regressor. The validation on applications from the MIBENCH and the PARSEC suites indicates significant gain in prediction accuracy compared to a purely quantitative characterization.
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Submitted on : Tuesday, December 10, 2019 - 10:09:43 AM
Last modification on : Tuesday, January 11, 2022 - 11:16:07 AM
Long-term archiving on: : Wednesday, March 11, 2020 - 3:48:47 PM


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  • HAL Id : hal-02401625, version 1


Cédric Courtaud, Julien Sopena, Gilles Muller, Daniel Gracia. Improving Prediction Accuracy of Memory Interferences for Multicore Platforms. RTSS 2019 - 40th IEEE Real-Time Systems Symposium, Dec 2019, Hong-Kong, China. ⟨hal-02401625⟩



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