B. Dufort and G. W. Roberts, On-chip analog signal generation for mixed-signal built-in self-test, IEEE Journal of Solid-State Circuits, vol.34, issue.3, pp.318-348, 1999.

M. Barragan, A fully-digital BIST wrapper based on ternary test stimuli for the dynamic test of a 40nm CMOS 18-bit stereo audio ?? ADC, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, issue.11, pp.1876-1888, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01447789

H. Chauhan, Accurate and efficient on-chip spectral analysis for built-in testing and calibration approaches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.3, pp.49-506, 2014.

F. Azais, Optimizing sinusoidal histogram test for low cost ADC BIST, Journal of Electronic Testing: Theory and Applications, vol.17, issue.3-4, pp.255-266, 2001.

G. Renaud, Fully differential 4-V output range 14.5-ENOB stepwise ramp stimulus generator for on-chip static linearity test of ADCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, issue.2, pp.281-293, 2019.
URL : https://hal.archives-ouvertes.fr/hal-01922278

A. Laraba, Exploiting pipeline ADC properties for a reduced-code linearity test technique, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.62, issue.10, pp.2391-2400, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01224434

T. Chen, USER-SMILE: Ultrafast stimulus error removal and segmented model identification of linearity errors for ADC built-in self-test, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.65, issue.7, pp.2059-2069, 2018.

M. J. Barragan, Practical simulation flow for evaluating analog/mixed-signal test techniques, IEEE Design & Test, vol.33, issue.6, pp.46-54, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01359611

S. Sunter, Using mixed-signal defect simulation to close the loop between design and test, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, issue.12, pp.2313-2322, 2016.

J. Huertas, Testable switched-capacitor filters, IEEE Journal of Solid-State Circuits, vol.28, issue.7, pp.719-724, 1993.

H. D. Stratigopoulos and Y. Makris, Concurrent detection of erroneous responses in linear analog circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.5, pp.878-891, 2006.

N. J. Stessman, System-level design for test of fully differential analog circuits, IEEE Journal of Solid-State Circuits, vol.31, issue.10, pp.1526-1534, 1996.

H. D. Stratigopoulos and Y. Makris, An adaptive checker for the fully differential analog code, IEEE Journal of Solid-State Circuits, vol.41, issue.6, pp.1421-1429, 2006.

V. and G. Gil, Assessing AMS-RF test quality by defect simulation, IEEE Transactions on Device and Materials Reliability, vol.19, issue.1, pp.55-63, 2019.