TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits

Jordan Locati (1, 2) , Christian Rivero (1) , Julien Delalleau , V. Della Marca (2) , Karine Coulié (2) , Jordan Innocenti (1) , Olivier Paulet (1) , Arnaud Regnier (1) , Stephan Niel (3)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 ST-CROLLES - STMicroelectronics [Crolles]

In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.

Mots clés: MOSFET architecture; junction engineering; junction breakdown

Domaines: Micro et nanotechnologies/Microélectronique

Jordan Locati, Christian Rivero, Julien Delalleau, V. Della Marca, Karine Coulié, et al.. TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits. 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2019, Udine, Italy. pp.1-4, ⟨10.1109/SISPAD.2019.8870384⟩. ⟨hal-02332336⟩