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Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

Abstract : This paper presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700-840 MHz at VDD = 1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 µW/MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.
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Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, et al.. Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Transactions on Circuits and Systems II: Express Briefs, Institute of Electrical and Electronics Engineers, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩. ⟨hal-02318785⟩

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