A flexible architecture for block turbo decoders using BCH or Reed-Solomon

Erwan Piriou (1) , Christophe Jego (2, 1) , Patrick Adde (1) , Michel Jezequel (1)

1 ELEC - Département Electronique
2 Lab-STICC_TB_CACS_IAS

In this paper, the first flexible architecture dedicated to block turbo decoders is presented The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors' knowledge, this is the first architecture implementing Reed-Solomon block turbo codes. This approach makes it possible to select the block turbo decoder architecture using optimum component codes in any circumstance. Our flexible elementary SISO decoder is dedicated to extended binary BCH codes (32,26) and (32,21) and to nonextended Reed-Solomon codes (31,29) and (31,27). Experimentation has been done on a Stratix-based NIOS development board.

Mots clés: Flexible architecture; BCH; Reed-Solomon; Block turbo decoder

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Erwan Piriou, Christophe Jego, Patrick Adde, Michel Jezequel. A flexible architecture for block turbo decoders using BCH or Reed-Solomon. IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe, Germany. ⟨10.1109/ISVLSI.2006.2⟩. ⟨hal-02194949⟩