Improving architecture efficiency of SoftCore processors

Bertrand Le Gal 1 Jego Christophe
1 IMS Laboratory
IMS - Laboratoire de l'intégration, du matériau au système
Abstract : The growing complexity of applications increases the challenge of the System-On-Chip design. The most efficient way to produce area and power efficient circuits is to design fully dedicated architectures for ASIC or FPGA technologies. However, such approach is unsuited with the “time to market” constraint due to times for design and verification. Moreover, this approach has a lack of flexibility: a modification in the application specification can require new design flow iterations. Another way to implement applications under “time to market” pressure is based on high-end processor usage. Nowadays, General-Purpose Processors (GPP) or Digital Signal Processors (DSP) provides high computation performance. Moreover, programming languages and compiler tools provide high flexibility degree for these approaches. However, general processors are not relevant in the embedded market.
Document type :
Conference papers
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https://hal.archives-ouvertes.fr/hal-02192235
Contributor : Axelle Pagnier <>
Submitted on : Tuesday, July 23, 2019 - 5:22:04 PM
Last modification on : Thursday, September 12, 2019 - 8:38:10 AM

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  • HAL Id : hal-02192235, version 1

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Bertrand Le Gal, Jego Christophe. Improving architecture efficiency of SoftCore processors. Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France. ⟨hal-02192235⟩

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