Certified and efficient instruction scheduling. Application to interlocked VLIW processors.

Cyril Six (1, 2) , Sylvain Boulmé (2) , David Monniaux (2)

1 Kalray
2 VERIMAG - IMAG - VERIMAG

CompCert is a moderately optimizing C compiler with a formal, machine-checked, proof of correctness: after successful compilation, the assembly code has a behavior faithful to the source code. Previously, it only supported target instruction sets with sequential semantics, and did not attempt reordering instructions for optimization. We present here a CompCert backend for a VLIW core (i.e. with explicit parallelism at the instruction level), the first CompCert backend providing scalable and efficient instruction scheduling. Furthermore, its highly modular implementation can be easily adapted to other VLIW or non-VLIW pipelined processors.

Mots clés: ormal verification of compiler optimizations; Instruction-level parallelism; theCoqproof assistant; Symbolic execution; Hash-consing

Domaines: Langage de programmation [cs.PL]; Logique en informatique [cs.LO]; Architectures Matérielles [cs.AR]

Cyril Six, Sylvain Boulmé, David Monniaux. Certified and efficient instruction scheduling. Application to interlocked VLIW processors.. Proceedings of the ACM on Programming Languages, 2020, OOPSLA 2020, pp.129. ⟨10.1145/3428197⟩. ⟨hal-02185883v3⟩